Introduction
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netX 50 to netX 51/52 | Migration Guide
DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public
2012-2013
1.3.1
netX Signal Description
General
PORn
Power on Reset
RSTINn Reset
Input
RSTOUTn Reset
Output
RDYn
RDY-LED / Boot option
RUNn
RUN-LED / Boot option
CLKOUT Clock
out
WDGACT Watchdog
active
Oscillator
OSC_XTI
25 MHz Crystal Input
OSC_XTO
25 MHz Crystal Output
OSC_VSS
Oscillator Power Supply Ground
OSC_VDDC
Oscillator Power Supply Core 1.5V
JTAG
JT_TRSTn JTAG
Test
Reset
JT_TMS
JTAG Test Mode Select
JT_TCLK JTAG
Test
Clock
JT_TDI
JTAG Test Data Input
JT_TDO
JTAG Test Data Output
SPI
SPI0_CLK
SPI 0 Clock
SPI0_CS0n
SPI 0 Chip Select 0
SPI0_CS1n
SPI 0 Chip Select 1
SPI0_MISO
SPI 0 Master Input Slave Output Data
SPI0_MOSI
SPI 0 Master Output Slave Input Data
QSPI_CLK
XiP / QSPI Clock
QSPI_CSn
XiP / QSPI Chip Select
QSPI_SIO0...3
XiP / QSPI Serial IO Data 0…3
I2C
I2C_SCL
I2C Serial Clock Line
I2C_SDA
I2C Serial Data Line
USB
USB_DNEG
USB D- Line
USB_DPOS
USB D+ Line
USB_VDDC
USB Power Supply Core 1.5 V
USB_VDDIO
USB Power Supply IO 3.3 V
Test
BSCAN_TRST Reset
Boundary Scan Controller
TEST
Activate Test Mode (left open)
TMC1
Test Mode 1 (left open)
TMC2
Test Mode 2 (left open)
