Package, Pinning, Pad Cells
29/56
netX 50 to netX 51/52 | Migration Guide
DOC120109MG05EN | Revision 5 | English | 2013-08 | Released | Public
2012-2013
Ball Pos
Signal
Pad Type
MUX-Func1
MUX-Func2
netX
netX
netX
netX
netX
50/51
52
50
51/52
50
51/52
50
51/52
50
51/52
H18 E18
DPM_D18
IOU9
G17 E17 DPM_D19/WDGACT
IOU9
B13 C12
DPM_D20
IOU9
A14 C11
DPM_D21
IOU9
A13 A11
DPM_D22
IOU9
C12 C10
DPM_D23
IOU9
B10 A9
DPM_D24
IOU9
A11 A8
DPM_D25
IOU9
A9 A6
DPM_D26
IOU9
C9 B7
DPM_D27
IOU9
B6 A2
DPM_D28
IOU9
A7 A4
DPM_D29
IOU9
A2 D3
DPM_D30
IOU9
J17 H17
DPM_D31
IOU9
C17 D16
DPM_INT*
DPM_DIRQn*
IOU9
B17 B15
DPM_RDn
IOU9
B18 C15
DPM_RDY* DPM_BUSYn*
IOU9
MII_RXCLK
C16 B14
DPM_WRn/WRLn
IOU9
B11 C8
TCLK DPM_SIRQn
IOU9
Table 14: Differences in Pinning and Pad Cells – Host Interface
Note:
* Only the name of these signals changed to be consistent with the configuration as
active low signals on Hilscher boards.
The Host Interface becomes two additional functions for serial data transfer between netX and
Host system. These are a very fast SPI slave interface and a MII interface. Both options are
activated by software and use an internal multiplexer to change the Host Interface signals. There
fore the signals are fixed and can not move to other pins.
The SPI slave works as Serial Port Memory means it can be read and write the internal Dual-Port
Memory without interfering the internal ARM CPU.
The Ethernet signals emulate a PHY with a MII Interface in the way that every CPU with an
integrated MAC can be used for data transfer.
