Host Interface
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COM-C | Communication Module
DOC021001DG12EN | Revision 12 | English | 2011-06 | Released | Public
© Hilscher, 2002-2011
No.
Description
Min.
Max.
Units
1
CS#, RD# low to BUSY# low
6
ns
2
Read Data available to BUSY# high
12
ns
4
BUSY# low width
0
3 - 7
CLK Cycle
5
CS#, WR# low to BUSY# low
6
ns
6
Write Data setup time to BUSY high
26
ns
8
BUSY# low width
0
3 - 7
CLK Cycle
CLK Cycle is 20.8 ns with 48 MHz CLK
Notes
Both CS# and RD# resp. CS# and WR# must be low to start a Dual-port memory cycle
If the CS# signal is going low or held low the BUSY# signal goes also low
Then after some clock cycle the BUSY# signal is released and going to high level
It's not possible to change the address lines with holding low the RD# or WR# signal low
The high level between two read and/or write cycles the RD# and WR# signals must be longer held at
high level than two CLK Cycle (41.6 ns)
Table 25: Symbols for COM Timing Diagram of a Read respectively Write Cycle at the Dual-Port Memory
