hilscher CIFX Series, User Manual

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PC Cards cifX Compact PCI, Mini PCI, Mini PCIe, PCI-104 | Installation, Operation and Hardware Description
DOC120205UM53EN | Revision 53 | English | 2019-03 | Released | Public
© Hilscher, 2008-2019
9.12.5 Pin Assignment for Mini PCI Express Bus, X1/X2 for 2 Channel
Devices
Only for
CIFX 90E-2DP\ET\F, CIFX 90E-2DP\MR\ET\F
CIFX 90E-2DP\CO\ET\F, CIFX 90E-2DP\CO\MR\ET\F
CIFX 90E-2DP\DN\ET\F, CIFX 90E-2DP\DN\MR\ET\F
CIFX 90E-2CO\ET\F, CIFX 90E-2CO\MR\ET\F
CIFX 90E-2CO\DN\ET\F, CIFX 90E-2CO\DN\MR\ET\F
CIFX 90E-2DN\ET\F, CIFX 90E-2DN\MR\ET\F (X3 and X4)
Pin Assignment Mini PCI Express Bus, X1/X2 for 2 Channel Devices
Pin (X1) Signal Pin (X2) Signal
51 (not used) 52 +3.3V
49 (not used) 50 GND
47 (not used)
48 (not used)
45 (not used) 46 (not used)
43 GND 44 (not used)
41 +3.3V 42 Bootstart
39 (not used) 40 GND
37 GND 38 USB_D+ ( disabled – not used )
35 GND 36 USB_D - ( disabled – not used )
33 PERp0
8
34 GND
31 PERn0
8
32 (not used)
29 GND 30 (not used)
27 GND 28 (not used)
25 PETp0
8
26 GND
23 PETn0
8
24 (not used)
21 GND 22 PERST#
19 (not used) 20 (not used)
17 (not used) 18 GND
15 GND 16 (not used)
13 14 (not used)
11 REFCLK- 12 (not used)
9 GND 10 (not used)
7 CLKREQ# 8 (not used)
5 (not used) 6 (not used)
3 (not used) 4 GND
1 (not used) 2 3.3V
Table 130: Pin Assignment Mini PCI Express Bus, X1/X2 for 2 Channel Devices
Unless otherwise noted, the pin assignment for Mini PCI Express bus,
X1/X2 described in
Table 130 corresponds to the bus specification for Mini
PCI Express [bus spec 6, Rev. 1.2, Section 3.3].
Note! Note the following characteristics for the pin assignment of the Mini
PCI Express Bus, X1/X2, described in Table 130 :
ƒ The Pins 6, 28, 48 and Pin 24 are ‘not used’ .
ƒ The Pins 36 and 38 are ‘not used’ .
ƒ The pin assignment of the Pin 42 deviates from the standard
specification Mini PCI Express. The Pins 44 and 46 are ‘not used’ .