Hand Held Products IT4000, Integration Manual

Page: 17 / 56

IMAGETEAM™ 4X00 Series Integration Manual 2 - 7
Timing Control LSB (Address O1)
Initial Hand Held Products Configuration Vertical Timing
Note the row/line data relationship within each frame. The data presented within each line is the data from that line. The IT4X00
Series engine does not present data rolled over from a previous frame, nor is data rolled back from a future frame (refer to
Vertical
Considerations , page 2-2).
Initial Hand Held Products Configuration Horizontal Row/Line Timing
Preliminary Intel PXA27X Interface
The Intel
®
PXA27X (Bulverde) integrates a CMOS imager interface on the chip that can be used to interface to the IT4X00 Series.
The interface uses a synchronization tracking timing circuit that is very flexible and relatively easy to use.
Reserved Reserved Reserved Reserved Reserved VSync Polarity HSync Polarity Reserved
0 0 0 1 1 0=Active Low
1=Active High 0=Active Low
1=Active High 1
Vert
Horz
Data
Vsync IRQ
0 1 2
479 520 524
First 5 light
shielded lines
35
blank
lines
Last 5
light
shielded
Active rows/lines 6 to 485
Hor
PxCLK
Data
640 Valid Data
208
858
First 5
light
shielded
pixels Last 5
light
shielded
pixels