GRUNDIG Service
GDP 2200
2 - 14
Name
Type
Pin
Description AML3250
Audio
adc
I
50
Audio data in
adata[3:0]
O
46, 47, 48, 49
Audio data out
alrclk
O
45
Left/right clock
amclk
O
52
Master clock
aoclk
O
44
Data clock
lec958
O
51
IEC958 output
aiclk_xin
I
89
Audio clock XTAL pin, Connect a 14.318MHz crystal or drive with an oscillator (5MHz to 40MHz).
aiclk_xout
O
90
Audio clock XTAL pin, Connect a 14.318MHz crystal. Can be left open if aiclk_xin is driven by an oscillator.
aud_pll_filt
O
72
Audio PLL filter pin (820pF to ground)
Video
avid[5:0]
O
*
Video encoder analog DAC output, pins: 55, 56, 59, 60, 64, 65
iref
O
57
Current reference
bias
O
58
Bias voltage
comp
O
61
Compensation
vclk
B
37
Video clock
vd[0]
B
40
Video D0, Address[8], UART RTS, GPIO[16].
vd[1]
B
41
Video D1, Address[9], UART RI, GPIO[17]
vd[2]
B
43
Video D2, Address[10], UART DTR, GPIO[18]
vd[3]
B
106
Video D3, Address[11], UART DSR, GPIO[19]
vd[4]
B
105
Video D4, Address[12], UART DCD, GPIO[20]
vd[5]
B
104
Video D5, Address[13], UART CTS, GPIO[21]
vd[6]
B
103
Video D6, Address[14], UART TxD, GPIO[22]
vd[7]
B
102
Video D7, Address[15], UART RxD, GPIO[23]
vhs_n
B
38
Horizontal sync
vvs_n
B
39
Vertical sync
DVD-DSP / IDE
cs0_n
O
188
Chip select 0
cs1_n
O
186
Chip select 1
csel
O
194
Cable select
da[2:0]
O
189, 190, 191
Address
dd[0]
B
202
IDE/DVD-DSP D0 (CD-Data in CD-DSP mode)
dd[1]
B
203
IDE/DVD-DSP D1 (CD-LRCLK in CD-DSP mode)
dd[2]
B
204
IDE/DVD-DSP D2 (CD-BCLK in CD-DSP mode)
dd[3]
B
205
IDE/DVD-DSP D3 (CD-C2PO in CD-DSP mode)
dd[7:4]
B
1, 2, 206, 207
IDE/DVD-DSP D[7:4]
dd[15:8]
B
3…5, 7…11
IDE D[15:8]
dior_n/sos
B
201
IDE dior_n, DVD-DSP sos
diordy/stb
I
198
IDE diordy, DVD-DSP strobe
diow_n/err
B
200
IDE diow_n, DVD-DSP error
dmack_n
O
185
IDE DMA acknowledge
dmarq/dack
I
197
IDE DMA request DVD-DSP dack
irq14
I
196
Interrupt HD0
irq15
I
195
Interrupt HD1
Other
VDD(core)
P
*
2.5V power supply, pins: 12, 26, 42, 54, 63, 66, 68, 69, 76, 91, 112, 131, 161, 169, 183, 192, 208
GND(core)
P
*
2.5V ground, pins: 6, 17, 20, 36, 53, 62, 67, 70, 71, 73, 75, 78, 79, 88, 107, 118, 136, 147, 165, 179, 187
VDD(pads)
P
*
3.3V power supply, pins: 23, 82, 124, 141, 175
GND(pads)
P
*
3.3V ground, pins: 31, 129, 173, 199
Le
O
193
No connect
reset_n
I
156
Active low chip RESET. This pin must be held low for at least 10ms after power has been supplied to the
chip. There are several pins that use the rising edge of this signal to configure the chip.
sclk_xin
I
80
MPEG clock XTAL pin. Connect a 14.318MHz crystal or drive with an oscillator (5MHz to 40MHz)
sclk_xout
O
81
MPEG clock XTAL pin, Connect a 14.318MHz crystal. Can be left open if sclk_xin is driven by an oscillator.
mpeg_pll_filt
O
77
MPEG PLL filter
arm_pll_filt
O
74
tck
I
158
JTAG, ICD, test pin
tdi
I
160
JTAG, ICD, test pin
tdo
B
157
JTAG, ICD, test pin
test_n
I
154
JTAG, ICD, test pin
tms
I
159
JTAG, ICD, test pin
trst_n
I
155
JTAG, ICD, test pin
