USB232 Converter User Guide
1-5
1.6 UART Manager
The UART Manager enables/disables the UART including the TX and RX FIFOs.
1.6.1 Transmitter
The transmitter consists of a 128-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out
packet has been received and the CRC has been validated, the data bytes in that packet are written into the
TX FIFO of the specified UART channel. Data from the TX FIFO is transferred to the TSR when the TSR is
idle or has completed sending the previous data byte. The TSR shifts the data out onto the TX output pin at
the data rate defined by the CLOCK_DIVISOR and TX_CLOCK_MASK registers. The transmitter sends
the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and
adds the stop-bit(s). The transmitter can be configured for 7 or 8 data bits with parity or 9 data bits with no
parity.
Internal
48MHz
Oscillator
USB Device
Interface
128-byte
TX FIFO
384-byte
RX FIFO
MODEM I/O
Internal
Status and
Control
Registers
Baud
Rate
Generator
UART
TX
RX
RTS
CTS
DTR
DSR
CD
RI
XR21V1410
Figure 2-UART Block Diagram
1.6.2 Receiver
The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in
the RSR via the RX pin is transferred into the RX FIFO along with any error tags such as Framing, Parity,
Break and Overrun errors. Data from the RX FIFO can be sent to the USB host by sending a bulk-in packet.
1.6.3 Automatic RTS/CTS Hardware Flow Control
Automatic RTS flow control is used to prevent data overrun errors in local RX FIFO by de-asserting the
RTS signal to the remote UART. When there is room in the RX FIFO, the RTS pin will be re-asserted.
Automatic CTS flow control is used to prevent data overrun to the remote RX FIFO. The CTS# input is
monitored to suspend/restart the local transmitter
.
1.6.4 Automatic DTR/DSR Hardware Flow Control
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control
described above except that it uses the DTR# and DSR# signals.
