5 Configuration Mode Introduction
5.2 JTAG Configuration
UG290-2.3E
27(87)
Figure 5-12 Read ID Code Data Register Access Timing
SRAM Configuration Process
The FPGA SRAM is configured using an external Host to enable the
FPGA functions. SRAM is configured via JTAG to avoid the influence of
Configuration Mode Pins.
Generate the FS file using Gowin software. Configure SRAM via JTAG.
The process of SRAM configuration using the external Host is as follows,
as shown in Figure 5-13.
1. Establish a JTAG link and reset TAP;
2. Read the device ID CODE and check if it matches.
3. Erase the SRAM if it has been configured.
Please refer to “
”.
4. Send the "0x15" instruction of ConfigEnable;
5. Send the "0x12" instruction of Address Initialize;
6. Send the "0x17" instruction of Transfer Configuration Data.
7. Move the state machine to Shift-DR (Data Register). Send
Configuration Data from the MSB bit by bit till all the bitstream file
content is sent.
8. Send the "0x3A" instruction of ConfigDisabled;
7. Send the "
0x02” instruction of Noop to end the configuration process.
8. Please refer to Process of Reading SRAM (The process of reading
SRAM) if reading back Configuration Data is required for verification.
