GOWIN GW1NSER Series User Manual Download Page 8 | Manualshive

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1 About This Guide

1.3 Terminology and Abbreviations

UG884-1.01E

2(14)

1.3

Terminology and Abbreviations

The terminology and abbreviations used in this manual are as shown in

Table 1-1 Terminology and Abbreviations

Terminology and Abbreviations

Full Name

FPGA

Field Programmable Gate Array

GPIO

Gowin Programmable IO

QN48P

QFN48P

QN48G

QFN48G

1.4

Support and Feedback

Gowin Semiconductor provides customers with comprehensive

technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.

Website: www.gowinsemi.com
E-mail:[email protected]

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Summary of Contents for GW1NSER Series

Page 1: ...GW1NSER series of SecureFPGA Package Pinout User Guide UG884 1 01E 04 16 2020 ...

Page 2: ...form or by any denotes electronic mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in th...

Page 3: ...Revision History Date Version Description 10 8 2019 1 0E Initial version published 04 16 2020 1 01E Quantity of GW1NSER 4C QN48P QN48G Pins modified ...

Page 4: ...ew 3 2 1 PB Free Package 3 2 2 Package and Max User I O Information 4 2 3 Power Pin 4 2 4 Pin Quantity 5 2 4 1 Quantity of GW1NSER 4C Pins 5 2 5 Pin Definitions 6 2 6 I O BANK Introduction 9 3 View of Pin Distribution 10 3 1 View of GW1NSER 4C Pins Distribution 10 3 1 1 View of QN48P Pins Distribution 11 3 1 2 View of QN48G Pins Distribution 12 4 Package Diagrams 13 4 1 QN48P QN48G Package Outline...

Page 5: ...s Figure 2 1 GW1NSER series of SecureFPGA products I O Bank Distribution 9 Figure 3 1 View of GW1NSER 4C QN48P Pins Distribution Top View 11 Figure 3 2 View of GW1N 4 QN48G Pins Distribution Top View 12 Figure 4 1 Package Outline of QN48P QN48G 14 ...

Page 6: ...e 2 1 Package Max User I O Information and LVDS Paris 4 Table 2 2 GW1NSER Power Pins 4 Table 2 3 Quantity of GW1NSER 4CPins 5 Table 2 4 Definition of the Pins in the GW1NSER series of SecureFPGA products 6 Table 3 1 Other pins in GW1NSER 4C QN48P 11 Table 3 2 Other pins in GW1NSER 4C QN48G 12 ...

Page 7: ...of pin numbers distribution of pins and package diagrams 1 2 Related Documents The user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS881 GW1NSER series of SecureFPGA products Data Sheet 2 UG290 Gowin FPGA Products Programming and Configuration User Guide 3 UG884 GW1NSER series of SecureFPGA products Package and Pinout 4 UG883 GW1NSER 4C ...

Page 8: ... Abbreviations Terminology and Abbreviations Full Name FPGA Field Programmable Gate Array GPIO Gowin Programmable IO QN48P QFN48P QN48G QFN48G 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways Website www gowinsemi com E mail support gow...

Page 9: ...curity library is provided with GOWIN SecureFPGA devices allowing easy integration of common security features into user applications The GOWIN SecureFPGA feature set is widely applicable and can used for a variety of consumer industrial IoT edge and server management applications 2 1 PB Free Package The GW1NSER series of SecureFPGA products are PB free in line with the EU ROHS environmental direc...

Page 10: ...al abbreviations are employed to refer to the package types See 1 3Terminology and Abbreviations The JTAGSEL_N and JTAG pins cannot be used as I O simultaneously The data in this table is when the loaded four JTAG pins TCK TDI TDO and TMS are used as I O When mode 2 0 001 JTAGSEL_N and the four JTAG pins TCK TDI TDO and TMS can be used as GPIO simultaneously and the Max user I O plus one 2 3 Power...

Page 11: ... 9 4 4 9 4 4 BANK3 11 5 0 11 5 0 Max User I O 2 38 38 Differential Pair 18 18 True LVDS output 4 4 VCC 2 2 VCCO0 1 1 VCCO1 1 1 VCCO2 1 1 VCCO3 2 2 VCCX 1 1 VSS 1 1 MODE0 0 0 MODE1 0 0 MODE2 0 0 JTAGSEL_N 1 1 Note Single end Differential I O quantity include CLK pins and download pins 2 The JTAGSEL_N and JTAG pins cannot be used as I O simultaneously The data in this table is when the loaded four J...

Page 12: ...e user I O These pins can be used as user I O when the functions are not used RECONFIG_N I internal weak pull up Start new GowinCONFIG mode when low pulse READY I O When high level the device can be programmed and configured When low level the device cannot be programmed and configured DONE I O High level indicates successful program and configure Low level indicates incomplete or failed to progra...

Page 13: ...CLKT_ x I Pins in global clock input T True x global clock No GCLKC_ x I Pins for Global clock input C Comp x global clock No LPLL_T_fb RPLL_T_fb I L R PLL feedback input pin T True LPLL_C_fb RPLL_C_fb I L R PLL feedback input pin C Comp LPLL_T_in RPLL_T_in I L R PLL clock input pin T True LPLL_C_in RPLL_C_in I L R PLL clock input pin C Comp CH 7 0 I Eight channel analog input MODE2 I internal wea...

Page 14: ...accuracy resistance XIN NA Crystal input signals XOUT NA Crystal oscillator signals IDPAD NA ID signal VBUSPAD NA VBUS signal VDDA NA Analog power supply voltage VDDA 3 3V VDDAUSB NA Analog power supply pin 3 3V VDDDUSB NA Analog power supply pin 3 3V VDDPL NA Power supply pin for driver 1 2V ...

Page 15: ...R series of SecureFPGA products The four I O Banks in the GW1NSER series of SecureFPGA products are marked with four different colors Various symbols are used for the user I O power and ground The various symbols and colors used for the various pins are defined as follows denotes the I O in BANK0 The filling color changes with the BANK denotes the I O in BANK1 The filling color changes with the BA...

Page 16: ...3 View of Pin Distribution 3 1 View of GW1NSER 4C Pins Distribution UG884 1 01E 10 14 3View of Pin Distribution 3 1 View of GW1NSER 4C Pins Distribution ...

Page 17: ...ER 4C Pins Distribution UG884 1 01E 11 14 3 1 1 View of QN48P Pins Distribution Figure 3 1 View of GW1NSER 4C QN48P Pins Distribution Top View Table 3 1 Other pins in GW1NSER 4C QN48P VCC 11 37 VCCO0 5 VCCO1 38 VCCO2 36 VCCO3 12 24 VCCX 25 VSS 26 ...

Page 18: ...NSER 4C Pins Distribution UG884 1 01E 12 14 3 1 2 View of QN48G Pins Distribution Figure 3 2 View of GW1N 4 QN48G Pins Distribution Top View Table 3 2 Other pins in GW1NSER 4C QN48G VCC 11 37 VCCO0 5 VCCO1 38 VCCO2 36 VCCO3 12 24 VCCX 25 VSS 26 ...

Page 19: ...4 Package Diagrams UG884 1 01E 13 14 4Package Diagrams ...

Page 20: ...re 4 1 Package Outline of QN48P QN48G PAD ZONE EXPOSED THERMAL BOTTOM VIEW 4 20 4 20 4 10 4 30 4 10 4 30 177 177 L F载体尺寸 MIL Ne 4 40BSC c 0 20 0 15 0 25 __ A1 0 05 0 02 0 85 6 00 6 10 e 0 40BSC E2 0 75 0 85 E D2 A D 0 23 0 18 0 20 b MAX NOM MIN MILLIMETER SYMBOL 5 90 6 10 6 00 5 90 L 0 45 0 35 0 40 0 30 0 40 h 0 35 4 40BSC Nd ...

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