GOWIN GW1NRF Series, User Manual

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2Overview 2.5 Pin Definitions
UG893-1.0E 6(12)
Pin Name I/O Description
output
Data port D1 in CPU mode
SI /D2 I/O
MISO in MSPI mode: Master data output/Slave
data input
Data port D2 in CPU mode
TMS
I, internal weak
pull-up
Serial mode input in JTAG mode
TCK I
Serial clock input in JTAG mode, which needs to be
connected with 4.7 K drop-down resistance on
PCB
TDI
I, internal weak
pull-up
Serial data input in JTAG mode
TDO O Serial data output in JTAG mode
JTAGSEL_N
I, internal weak
pull-up
Select signal in JTAG mode, active-low
SCLK I Clock input in SSPI, SERIAL, and CPU mode
DIN
I, internal weak
pull-up
Input data in SERIAL mode
DOUT O Output data in SERIAL mode
CLKHOLD_N
I, internal weak
pull-up
High level, SCLK will be connected internally in
SSPI mode or CPU mode
Low level, SCLK will be disconnected from SSPI
mode or CPU mode
WE_N I Select data input/output of D[7:0] in CPU mode
GCLKT_[x] I
Pins in global clock input, T(True), [x]: global clock
No.
GCLKC_[x] I
Pins for Global clock input, C(Comp), [x]: global
clock No.
LPLL_T_fb/RPLL_T_fb I
Left/Right PLL feedback input pins, T(True)
LPLL_C_fb/RPLL_C_fb I Left/Right PLL feedback input pins, C(Comp)
LPLL_T_in/RPLL_T_in I
Left/Right PLL clock input pin, T(True)
LPLL_C_in/RPLL_C_in I Left/Right PLL clock input pin, C(Comp)
MODE2
I, internal weak
pull-up
GowinCONFIG modes selection pin.
MODE1
I, internal weak
pull-up
GowinCONFIG modes selection pin.
MODE0
I, internal weak
pull-up
GowinCONFIG modes selection pin.
Other Pins
NC NA Reserved.
VSS NA Ground pins
VCC NA Power supply pins in the internal core logic.
VCCO# NA Power supply pins in I/O voltage of I/O BANK#.
VCCX NA Power supply pins in auxiliary voltage.