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GOWIN GW1NRF Series, User Manual

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GOWIN GW1NRF Series User Manual Download Page 1

 

 

 

 

 

 

 

 

 

 
 

 

GW1NRF series of Bluetooth FPGA Products

 

 

Package and Pinout User Guide

 

 

 

 

UG893-1.0E, 11/12/2019 

 

 

 

Summary of Contents for GW1NRF Series

Page 1: ...GW1NRF series of Bluetooth FPGA Products Package and Pinout User Guide UG893 1 0E 11 12 2019 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...Revision History Date Version Description 11 12 2019 1 0E Initial version published ...

Page 4: ...ew 3 2 1 PB Free Package 3 2 2 Package Max User I O Information and LVDS Paris 3 2 3 Power Pin 4 2 4 Pin Quantity 4 2 4 1 Quantity of GW1NRF 4B Pins 4 2 5 Pin Definitions 5 2 6 I O BANK Introduction 7 3 View of Pin Distribution 8 3 1 View of GW1NRF 4B Pins Distribution 9 3 1 1 View of QN48 Pins Distribution 9 3 1 2 View of QN48E Pins Distribution 10 4 Package Diagrams 11 4 1 QN48 Package Outline 6...

Page 5: ...ures Figure 2 1GW1NRF series of Bluetooth FPGA products I O Bank Distribution 7 Figure 3 1 View of GW1NRF 4B QN48 Pins Distribution Top View 9 Figure 3 2 View of GW1NRF 4B QN48E Pins Distribution Top View 10 Figure 4 1 Package Outline QN48 12 ...

Page 6: ...Package Max User I O Information and LVDS Paris 3 Table 2 2 Other Pins in the GW1NRF Series 4 Table 2 3 Quantity of GW1NRF 4BPins 4 Table 2 4 Definition of the Pins in the GW1NRF series of Bluetooth FPGA products 5 Table 3 1 Other pins in GW1NRF 4B QN48 9 Table 3 2 Other pins in GW1NRF 4B QN48 10 ...

Page 7: ...lated documents at www gowinsemi com 1 DS891 GW1NRF series of Bluetooth FPGA products Data Sheet 2 UG290 Gowin FPGA Products Programming and Configuration User Guide 3 UG893 GW1NRF series of Bluetooth FPGA products Package and Pinout 4 UG892 GW1NRF 4B Pinout 1 3 Terminology and Abbreviations The terminology and abbreviations used in this manual are as shown in Table 1 1 below Table 1 1 Abbreviatio...

Page 8: ...upport and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways Website www gowinsemi com cn E mail support gowinsemi com ...

Page 9: ...age The GW1NRF series of Bluetooth FPGA products are PB free in line with the EU ROHS environmental directives The substances used in the GW1NRF series of Bluetooth FPGA products are in full compliance with the IPC 1752 standards 2 2 Package Max User I O Information and LVDS Paris Table 2 1 Package Max User I O Information and LVDS Paris Package Pitch mm Size mm GW1NRF 4B QN48 0 4 6 x 6 25 4 QN48E...

Page 10: ...er I O 2 25 25 Differential Pair 10 10 True LVDS output 4 4 VCC 2 2 VCCX 1 1 VCCO0 VCCO33 1 1 VCCO1 VCCO23 1 1 VSS 2 1 MODE0 0 0 MODE1 0 0 MODE2 0 0 JTAGSEL_N 1 1 Note 1 The number of single end differential LVDS I O includes CLK pins and download pins 2 The JTAGSEL_N and JTAG pins cannot be used as I O simultaneously The data in this table is when the loaded four JTAG pins TCK TDI TDO and TMS are...

Page 11: ...pose user I O These pins can be used as user I O when the functions are not used RECONFIG_N I internal weak pull up Start new GowinCONFIG mode when low pulse READY I O High level indicates the device can be programmed and configured currently Low level indicates the device cannot be programmed and configured currently DONE I O High level indicates successful program and configure Low level indicat...

Page 12: ...connected internally in SSPI mode or CPU mode Low level SCLK will be disconnected from SSPI mode or CPU mode WE_N I Select data input output of D 7 0 in CPU mode GCLKT_ x I Pins in global clock input T True x global clock No GCLKC_ x I Pins for Global clock input C Comp x global clock No LPLL_T_fb RPLL_T_fb I Left Right PLL feedback input pins T True LPLL_C_fb RPLL_C_fb I Left Right PLL feedback i...

Page 13: ...cts The four I O Banks that form the GW1NRF series of Bluetooth FPGA products are marked with four different colors Various symbols are used for the user I O power and ground The various symbols and colors used for the various pins are defined as follows denotes the I O in BANK0 The filling color changes with the BANK denotes the I O in BANK1 The filling color changes with the BANK denotes the I O...

Page 14: ...3View of Pin Distribution 2 6 I O BANK Introduction UG893 1 0E 8 12 3View of Pin Distribution ...

Page 15: ...tribution UG893 1 0E 9 12 3 1 View of GW1NRF 4B Pins Distribution 3 1 1 View of QN48 Pins Distribution Figure 3 1 View of GW1NRF 4B QN48 Pins Distribution Top View Table 3 1 Other pins in GW1NRF 4B QN48 VCC 11 37 VCCX 36 VCCO0 VCCO3 1 VCCO1 VCCO2 25 VSS 26 2 ...

Page 16: ... GW1NRF 4B Pins Distribution UG893 1 0E 10 12 3 1 2 View of QN48E Pins Distribution Figure 3 2 View of GW1NRF 4B QN48E Pins Distribution Top View Table 3 2 Other pins in GW1NRF 4B QN48 VCC 11 37 VCCX 36 VCCO0 VCCO3 1 VCCO1 VCCO2 25 VSS 26 ...

Page 17: ...4Package Diagrams UG893 1 0E 11 12 4Package Diagrams ...

Page 18: ...4 1 Package Outline QN48 PAD ZONE EXPOSED THERMAL BOTTOMVIEW 4 20 4 20 4 10 4 30 4 10 4 30 177 177 L F载体尺寸 MIL Ne 4 40BSC c 0 20 0 15 0 25 __ A1 0 05 0 02 0 85 6 00 6 10 e 0 40BSC E2 0 75 0 85 E D2 A D 0 23 0 18 0 20 b MAX NOM MIN MILLIMETER SYMBOL 5 90 6 10 6 00 5 90 L 0 45 0 35 0 40 0 30 0 40 h 0 35 4 40BSC Nd ...

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