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GOWIN DK USB2.0 GW2AR-LV18QN88PC8I7 GW1NSR-LV4CMG64PC7I6 V3.0, User Manual

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GOWIN DK USB2.0 GW2AR-LV18QN88PC8I7 GW1NSR-LV4CMG64PC7I6 V3.0 User Manual Download Page 17

3 Development Board Circuit 

3.3 Power Supply 

 

DBUG408-1.0E 

10(16) 

 

Signal Name 

FPGA Pin No. 

BANK 

I/O Level 

Description 

F1_TDI 

E2 

0 

3.3V 

JTAG Signal 

F1_TMS 

D2 

0 

3.3V 

JTAG Signal 

3.3

 

Power Supply 

3.3.1

 

Introduction 

The development board is powered via a power adapter. The input 

parameter is 100-240V~50/60MHz 25VA, and the output is DC +5V 2A. 

The input 5V power can generate 3.3V, 1.8V, 1.2V, and 1.0V via the 

power supply chip on the development board. 

 

Use two FP6165ADXR-G1 power chips to generate 1.2V and 1.0V 
power, and the maximum output current is 3A. 

 

Use one PAM2306AYPAA DC-DC power chip to generate 3.3V and 
1.8V power, and the maximum output current is 1A. 

3.4

 

Clock and Reset 

3.4.1

 

Introduction 

The development board offers a 12MHz oscillator connecting to the 

global clock pins and 8.192MHz IIS clock for 
FPGA-GW1NSR-LV4CMG64P at the same time. 

The development board offers a 12MHz oscillator connecting to the 

global clock pins and 8.192MHz IIS clock for FPGA-GW2AR-LV18QN88P 
at the same time. 

The development board resets through the key, and press the key to 

reset FPGA after power up. 

Figure 3-2 Connection Diagram of Clock and Reset 

KEY1

12MHz

RST_N

CLK_G

 

Summary of Contents for DK USB2.0 GW2AR-LV18QN88PC8I7 GW1NSR-LV4CMG64PC7I6 V3.0

Page 1: ...DK_USB2 0_GW2AR LV18QN88PC7I6_GW 1NSR LV4CMG64PC7I6_V3 0 User Guide DBUG408 1 0E 07 15 2022 ...

Page 2: ... any denotes electronic mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEM...

Page 3: ...Revision History Date Version Description 07 15 2022 1 0E Initial version published ...

Page 4: ...1 4 Support and Feedback 2 2 Development Board Introduction 3 2 1 Overview 3 2 2 A Development Board Kit 4 2 3 PCB Components 6 2 4 System Block Diagram 6 2 5 Features 7 3 Development Board Circuit 8 3 1 FPGA Module 8 3 2 Download Module 8 3 2 1 Introduction 8 3 2 2 Pinout 9 3 3 Power Supply 10 3 3 1 Introduction 10 3 4 Clock and Reset 10 3 4 1 Introduction 10 3 4 2 Pinout 11 ...

Page 5: ... 3 5 USB 2 0 interface 11 3 5 1 Introduction 11 3 5 2 Pinout 11 3 6 GPIO 13 3 6 1 Introduction 13 3 6 2 Pinout 14 3 7 LED Module 15 3 7 1 Introduction 15 3 7 2 Pinout 15 3 8 Keys Module 15 3 8 1 Introduction 15 3 8 2 Pinout 16 ...

Page 6: ...oard Suite 5 Figure 2 3 PCB Components 6 Figure 2 4 System Block Diagram 6 Figure 3 5 Connection Diagram of FPGA Download and Configuration 9 Figure 3 6 Connection Diagram of Clock and Reset 10 Figure 3 7 Connection Diagram of FPGA and USB 2 0 Interface 11 Figure 3 8 Connection Diagram of GPIO 13 Figure 3 9 Connection Diagram of LED 15 Figure 3 10 Key Circuit 16 ...

Page 7: ...P Clock and Reset Pinout 11 Table 3 8 GW2AR LV18QN88P Clock and Reset Pinout 11 Table 3 9 GW1NSR LV4CMG64P USB 2 0 Module Pinout 11 Table 3 10 GW2AR LV18QN88P USB 2 0 Module Pinout 12 Table 3 11 GW1NSR LV4CMG64P GPIO Pinout 14 Table 3 12 GW2AR LV18QN88P GPIO Pinout 14 Table 3 13 GW1NSR LV4CMG64P LED Pinout 15 Table 3 14 GW2AR LV18QN88P LED Pinout 15 Table 3 15 GW1NSR LV4CMG64P Keys Module Pinout 1...

Page 8: ...troduction to the functions circuits and pinouts of each module 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS226 GW2AR series of FPGA Products Data Sheet 2 UG115 GW2AR 18 Pinout 3 UG229 GW2AR series of FPGA Products Package and Pinout User Guide 4 DS861 GW1NSR series of FPGA Products Data Sheet 5 UG8...

Page 9: ... Flash Memory FPGA Field Programmable Gate Array GPIO Gowin Programmable I O LDO Low Dropout Regulator LUT4 4 input Look up Table LVDS Low Voltage Differential Signaling SSRAM Shadow Static Random Access Memory 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directl...

Page 10: ... DK_USB2 0_GW2AR LV18QN88PC8I7_GW1NSR LV4CMG64PC7I6 _V3 0 development board can apply to USB 2 0 communication USB communication test the function evaluation of GW1NSR 4C and GW2AR 18 series of FPGA hardware reliability verification and software learning and debugging The development board uses Gowin GW2AR LV18QN88P FPGA products which are the first generation products of the Arora family As a ...

Page 11: ...integrates GW1NS series of FPGA products and PSRAM chips The GW1NSR series of products include GW1NSR 2C and GW1NSR 2 devices GW1NSR 2C devices are embedded with ARM Cortex M3 hard core processor In addition the GW1NSR series of FPGA products are also embedded with USB2 0PHY user flash and ADC The development board equipped with a USB PHY chip supports 480Mbps high speed HS and 12Mbps full speed F...

Page 12: ...roduction 2 2 A Development Board Kit DBUG408 1 0E 5 16 Figure 2 2 A Development Board Suite 1 2 3 DK_Motor_GW2A LV55PG484C8I7_V3 0 development board USB Mini B data cable 5V power Input 100 240V 50 60Hz 0 5A Output DC 5V 2A ...

Page 13: ... 3 PCB Components Power 5V IN GPIO FPGA 1 8V 3 3V 1 0V Key JTAG OSC MODE USB2 0 USB2 0 Flash JTAG Key FPGA OSCGPIO 1 2V 2 4 System Block Diagram Figure 2 4 System Block Diagram GW2AR LV8QN88PC8I7 GW1NSR LV4CMG64PC7I6 USB2 0 USB2 0 LED KEY CLK LED KEY CLK JTAG FLASH JTAG IO IO 5V 3 3V 1 8V 1 2V 1 0V ...

Page 14: ...t board 3 Power External DC 5V 2A The green POWER light is on after power on The development board generates 5V 3 3V 1 8V 1 2V 1 0V and 1 0V 4 Clock system 12MHz crystal oscillator input 5 Memory Device 64Mbit FLASH 6 USB 2 0 interface One USB 2 0 interface communicates with GW2AR LV18QN88P One USB 2 0 interface communicates with GW1NSR LV4CMG64P 7 GPIO Interface GPIO interface enable communicatio...

Page 15: ...for more details For the I O BANK package and pinout information see UG863 GW1NSR Series of FPGA Products Package and Pinout User Guide for more details 3 2 Download Module 3 2 1 Introduction The development board provides a JTAG download interface You can set the MODE value to download the programs to the on chip SRAM or external Flash When downloaded to SRAM the bitstream file will be lost if th...

Page 16: ...K JTAG_TCK JTAG_TDO JTAG_TDI JTAG_TMS JTAG Interface Configuration FLASH 3 2 2 Pinout Table 3 1 FPGA GW2AR LV18QN88P Download and Configuration Pinout Signal Name FPGA Pin No BANK I O Level Description F2_TCK 6 2 1 8V JTAG Signal F2_TDO 8 2 1 8V JTAG Signal F2_TDI 7 2 1 8V JTAG Signal F2_TMS 5 2 1 8V JTAG Signal MSPI_DO 62 3 3 3V Configure FLASH Signal MSPI_DI 61 3 3 3V Configure FLASH Signal MSPI...

Page 17: ...to generate 1 2V and 1 0V power and the maximum output current is 3A Use one PAM2306AYPAA DC DC power chip to generate 3 3V and 1 8V power and the maximum output current is 1A 3 4 Clock and Reset 3 4 1 Introduction The development board offers a 12MHz oscillator connecting to the global clock pins and 8 192MHz IIS clock for FPGA GW1NSR LV4CMG64P at the same time The development board offers a 12MH...

Page 18: ...llator input F2_IIS_CLK 35 4 3 3V 8 192MHz F2_RST_N 19 6 3 3V 2 5V Reset Signal active low 3 5 USB 2 0 interface 3 5 1 Introduction USB 2 0 interface is directly connected to FPGA through configuration resistor The connection diagram is as shown in Figure 3 3 Figure 3 3 Connection Diagram of FPGA and USB 2 0 Interface PULLIP USB_D _CN USB_D _CP USB_TERM_P USB_D _CP USB_TERM_N USB_D USB_D USB_D _CN...

Page 19: ...US_DETECT_1N G2 2 3 3V VBUS disconnect detection to reset USB Table 3 6 GW2AR LV18QN88P USB 2 0 Module Pinout Signal Name FPGA Pin No BANK I O Level Description 2A_Pullip 80 0 3 3V Pull up USB_2A_D _CP 77 1 3 3V USB signal USB_2A_D _CN 76 1 3 3V USB Reference signal USB_2A_D _CP 71 1 3 3V USB signal USB_2A_D _CN 70 1 3 3V USB Reference signal 2A_Term_p 75 1 3 3V Terminal resistance control at high...

Page 20: ... the development board including eight 3 3V pins four ground pins fourteen GW1NSR LV4CMG64P pins and fourteen GW2AR LV18QN88P pins The connection diagram is as shown in Figure 3 4 Figure 3 4 Connection Diagram of GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 Pin Header GPIO10 GPIO11 GPIO12 GPIO13 ...

Page 21: ...O8 1N_GPIO9 A6 1 3 3V GPIO9 1N_GPIO10 B7 1 3 3V GPIO10 1N_GPIO11 A7 1 3 3V GPIO11 1N_GPIO12 A8 1 3 3V GPIO12 1N_GPIO13 B8 1 3 3V GPIO13 Table 3 8 GW2AR LV18QN88P GPIO Pinout Signal Name FPGA Pin No BANK I O Level Description 2A_GPIO0 42 4 3 3V GPIO0 2A_GPIO1 41 4 3 3V GPIO1 2A_GPIO2 40 4 3 3V GPIO2 2A_GPIO3 39 4 3 3V GPIO3 2A_GPIO4 38 4 3 3V GPIO4 2A_GPIO5 37 4 3 3V GPIO5 2A_GPIO6 33 5 3 3V GPIO6 ...

Page 22: ...am is as shown in Figure 3 5 Figure 3 5 Connection Diagram of LED LED2 3 3V 3 7 2 Pinout Table 3 9 GW1NSR LV4CMG64P LED Pinout Signal Name FPGA Pin No BANK I O Level Description F1_LED G1 2 3 3V LED 1 Table 3 10 GW2AR LV18QN88P LED Pinout Signal Name FPGA Pin No BANK I O Level Description F2_LED 13 6 3 3V LED 2 3 8 Keys Module 3 8 1 Introduction The development board has two keys that can be used ...

Page 23: ...Key Circuit KEY2 3 8 2 Pinout Table 3 11 GW1NSR LV4CMG64P Keys Module Pinout Signal Name FPGA Pin No BANK I O Level Description F1_RST_N A5 1 3 3V KEY1 Table 3 12 GW2AR LV18QN88P Key Module Pinout Signal Name FPGA Pin No BANK I O Level Description F2_RST_N 19 6 3 3V 2 5V KEY2 ...

Page 24: ......

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