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GOWIN DK START GW1NSR-LV4CQN48PC7I6 V 1.1, User Manual

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GOWIN DK START GW1NSR-LV4CQN48PC7I6 V 1.1 User Manual Download Page 3

 

 

Revision History 

Date 

Version 

Description 

01/21/2021 

1.0E 

Initial version published. 

07/30/2021 

1.1E 

The Quick Start in 2.2 A Development Board Suite deleted. 

Summary of Contents for DK START GW1NSR-LV4CQN48PC7I6 V 1.1

Page 1: ...DK_START_GW1NSR LV4CQN48PC7I6_V 1 1 User Guide DBUG388 1 1E 07 30 2021 ...

Page 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Page 3: ...Revision History Date Version Description 01 21 2021 1 0E Initial version published 07 30 2021 1 1E The Quick Start in 2 2 A Development Board Suite deleted ...

Page 4: ...Board Introduction 3 2 1 Overview 3 2 2 A Development Board Suite 4 2 3 PCB Components 5 2 4 System Block Diagram 5 2 5 Features 6 2 6 Development Board Specification 7 3 Development Board Circuit 9 3 1 FPGA Module 9 3 2 Download Debug 9 3 2 1 Overview 9 3 2 2 USB 10 3 2 3 J LINK 10 3 2 4 Procedure 10 3 2 5 Pinout 11 3 3 Power Supply 11 3 3 1 Overview 11 3 3 2 Power System Distribution 11 3 3 3 Po...

Page 5: ... 13 3 6 Switches 13 3 6 1 Overview 13 3 7 Key 14 3 7 1 Overview 14 3 7 2 Key Circuit 14 3 7 3 Pinout 14 3 8 GPIO 14 3 8 1 Overview 14 3 8 2 GPIO Circuit 15 3 8 3 Pinout 15 3 9 MIPI LVDS 15 3 9 1 Overview 15 3 9 2 MIPI LVDS Circuit 16 3 9 3 Pinout 16 3 10 RS232 18 3 10 1 Overview 18 3 10 2 RS232 Circuit 18 3 10 3 Pinout 19 4 Considerations 20 5 Gowin Software 21 ...

Page 6: ... PCB Components 5 Figure 2 4 System Block Diagram 5 Figure 3 1 FPGA and USB Connection Diagram 10 Figure 3 2 FPGA and J LINK Connection Diagram 10 Figure 3 3 Power System Distribution 11 Figure 3 4 Clock Reset 12 Figure 3 5 LED Circuit 13 Figure 3 6 Key Circuit Diagram 14 Figure 3 7 GPIO Circuit 15 Figure 3 8 LVDS Circuit 16 Figure 3 9 RS232 Download Connection 18 ...

Page 7: ...ent Board Specification 7 Table 3 1 FPGA Download Pinout 11 Table 3 2 FPGA Power Supply Pinout 12 Table 3 3 FPGA Clock and Reset Pinout 12 Table 3 4 LED Pinout 13 Table 3 5 Key Circuit Pinout 14 Table 3 6 J17 GPIO Pinout 15 Table 3 7 J15 FPGA Pinout 16 Table 3 8 J16 FPGA Pinout 17 Table 3 9 RS232 Pinout 19 ...

Page 8: ...o the function circuit and Pinout of each module 3 Attentions in use of the development board 4 An introduction to the usage of the FPGA development software 1 2 Related Documents You can find the related documents at www gowinsemi com 1 DS821 GW1NS series FPGA Products Data Sheet 2 UG823 GW1NS series of FPGA Products Package and Pinout Manual 3 UG824 GW1NS 4 4C Pinout 4 UG290 Gowin FPGA Products ...

Page 9: ...GPIO Gowin Programmable Input output MCU Microprogrammed Control Unit USB Universal Serial Bus SoC System On Chip JTAG Joint Test Action Group SRAM Static Random Access Memory RS232 Recommend Standard 232 ARM Advanced RISC Machines BSRAM Block SRAM SPI Serial Peripheral Interface PLL Phase locked Loop QN48 QFN48 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive tec...

Page 10: ...ssor and the GW1NSER 4C offers one time programming and authentication code features 2 1 Overview Figure 2 1 DK_START_GW1NSR LV4CQN48PC7I6_V1 1 Development Board The development board adopts the GW1NSR 4C SoC FPGA SoC FPFA is embedded with an ARM Cortex M3 hard core processor When the ARM Cortex M3 hard core processor is employed as the core the needs of the Min memory can be met FPGA logic resour...

Page 11: ...ant package types among other benefits The development board offers abundant external interfaces including MIPI LVDS interfaces GPIO interfaces etc There are also button LED and other resources for developers or fans to learn to use 2 2 A Development Board Suite A development board suite includes the following items DK_START_GW1NSR LV4CQN48PC7I6_V1 1 development board USB Mini Data Line Figure 2 2...

Page 12: ...8V LVDS MIPI Input 5V IN Download Key OSC GPIO UA RT LVDS MIPI Output J Link MCU Debug USB J Link Select FPGA Reset 2 4 System Block Diagram Figure 2 4 System Block Diagram J Link LDO 1 2V 1 8V 2 5V 3 3V 1 BUTTON OSC 50MHz FT232HL GPIO 1 LED MINI USB 4 SWITCH 5V 5 Pairs LVDS MIPI INPUT 4Pairs LVDS MIPI OUTPUT 1 UART 1 SPI Flash FPGA ...

Page 13: ...es and capacities of B SRAM 2 FPGA Configuration Modes JTAG AUTO BOOT 3 Clock resource 50MHz Clock Crystal Oscillator 4 Key switch and slide switch One reset button One key switch 5 LED One power indicator green 1 LEDs green One Key indicator green 6 Memory 1Mbit embedded Flash 64Mbit external SPI Flash 7 MIPI LVDS Five pairs of LVDS differential input Four pairs of LVDS differential output 8 GPIO...

Page 14: ...oad circuit and other circuits via 5V 3 3 V circuit Provide power for FPGA via 5V to 2 5V circuit Provide power for FPGA via 5V 1 8V circuit Provide power for FPGA via 5 V 1 2 V circuit 4 Key Switches Available for testing 1 5 Reset button Reset for FPGA 1 6 LED Test indicator Key indicator Power indicator Four Test indicators green One Power indicator green One Key indicator green 7 Crystal Oscil...

Page 15: ...ction USB interface ESD protection Power interface Inverse current and over current protection USB interface ESD protection 15kV non contact discharge 8kV contact discharge Schottky diode is connected between positive and negative anodes of power interface 2A self recovery fuses are connected at power inlet 13 Voltage Input Voltage 5V 14 Humidity 95 15 Temperature Operating range 20 70 ...

Page 16: ...mation please refer to UG863 GW1NSR series of FPGA Products Package and Pinout User Guide 3 2 Download Debug 3 2 1 Overview The development board provides a USB interface and a J Link interface The fs file can be downloaded to the internal SRAM or internal Flash as needed Note When downloaded to SRAM the data stream file will be lost if the device is powered down and it will need to be downloaded ...

Page 17: ...K Connection Diagram TMS TCK TDI TDO 20PIN_2 54mm pitch Double Row Pin 7 6 3 4 U1 J8 GW1NSR LV4CQN48PC7I6_V1 1 3 2 4 Procedure 1 FPGA and MCU Download Mode Plug the USB cable to the development board USB interface J6 Note Before downloading switch the SW3 SW4 SW5 and SW6 on the development board to FT232 side 2 MCU Debugging Mode Connect to J8 with the J Link simulator Note Before Debugging switch...

Page 18: ... 5V 1 2V DONE 9 0 One DONE indicator 3 3V 2 5V 1 2V 3 3 Power Supply 3 3 1 Overview DC5V is input by USB interface The TI LDO power supply chip is used to step down voltage from 5V to 3 3V 2 5V 1 8V and 1 2V which can meet the power demand of the development board 3 3 2 Power System Distribution Figure 3 3 Power System Distribution USB Interface DC5V Input TPS7A7001 LDO 1 2V TPS7A7001 LDO 3 3V TPS...

Page 19: ...D 3 4 Clock Reset 3 4 1 Overview The development board provides a 50MHz crystal oscillator connected to the PLL input pin This can be employed as the input clock for the PLL in FPGA Frequency division and multiplication of PLL can output the clock required by the user 3 4 2 Clock Reset Figure 3 4 Clock Reset 22 23 KEY2 50MHz ADM811 3 3V F_RST_N F_CLK U1 U2 X2 GW1NSR LV4CQN48PC7I6_V1 1 SN74 AVC4 T2...

Page 20: ...ays When the FPGA corresponding pin output signal is logic low the LED is lit If the signal is high LED is off 3 5 2 LED Circuit Figure 3 5 LED Circuit LED1 33 VCC3P3 F_LED1 GW1NSR LV4CQN48PC7I6_V1 1 U1 3 5 3 Pinout Table 3 4 LED Pinout Signal Name Pin No BANK Description I O Level F_LED1 33 2 LED1 2 5V 1 2V 3 6 Switches 3 6 1 Overview There are four slide switches in the development board to cont...

Page 21: ...PGA pins for testing purposes 3 7 2 Key Circuit Figure 3 6 Key Circuit Diagram KEY1 KEY1 VCC3P3 21 F_KEY1 U1 GW1NSR LV4CQN48PC7I6_V1 1 SN74A VC4T2 45 U26 3 7 3 Pinout Table 3 5 Key Circuit Pinout Signal Name Pin No BANK Description I O Level F_KEY1 21 2 KEY1 1 8V 3 8 GPIO 3 8 1 Overview One 6P double column pins with 2 54mm pitch is reserved on the development board for user testing ...

Page 22: ...ignal Name Pin No Socket Pin No BANK Description I O Level H_B_IO7 8 1 0 General I O 2 5V 1 8V 1 2V H_B_IO8 1 2 0 General I O 2 5V 1 8V 1 2V H_B_IO9 2 3 0 General I O 2 5V 1 8V 1 2V 4 GND GND 5 GND GND 6 GND GND 3 9 MIPI LVDS 3 9 1 Overview Two 10P double columns with 2 mm pitch are reserved on the development board for MIPI LVDS input output testing and high speed data communication ...

Page 23: ...F_LVDS_B3_N F_LVDS_B4_N F_LVDS_B5_N J16 3 9 3 Pinout Table 3 7 J15 FPGA Pinout Signal Name FPGA Pin No Socket Pin No BANK Description I O Level F_LVDS_A1_P 28 1 2 Differential output channel 1 2 5V LVDS 1 2V MIPI F_LVDS_A1_N 27 2 2 Differential output channel 1 2 5V LVDS 1 2V MIPI GND 3 GND 4 F_LVDS_A2_P 30 5 2 Differential output channel 2 2 5V LVDS 1 2V MIPI F_LVDS_A2_N 29 6 2 Differential outpu...

Page 24: ...FPGA Pinout Signal Name FPGA Pin No Socket Pin No BANK Description I O Level F_LVDS_B1_P 48 1 1 Differential input channel 1 2 5V 1 2V LVDS MIPI F_LVDS_B1_N 47 2 1 Differential input channel 1 2 5V 1 2V LVDS MIPI GND 3 GND 4 F_LVDS_B2_P 46 5 1 Differential input channel 2 2 5V 1 2V LVDS MIPI F_LVDS_B2_N 45 6 1 Differential input channel 2 2 5V 1 2V LVDS MIPI GND 7 GND 8 F_LVDS_B3_P 44 9 1 Differen...

Page 25: ... MIPI GND 15 GND 16 F_LVDS_B5_P 40 17 1 Differential input channel 5 2 5V 1 2V LVDS MIPI F_LVDS_B5_N 39 18 1 Differential input channel 5 2 5V 1 2V LVDS MIPI GND 19 GND 20 3 10 RS232 3 10 1 Overview One RS232 interface is reserved on the development board for the FPGA to communicate with PC or the other devices 3 10 2 RS232 Circuit Figure 3 9 RS232 Download Connection UART_TXD UART_RXD DB9 UART_TX...

Page 26: ...oard Circuit 3 10 RS232 DBUG388 1 1E 19 21 3 10 3 Pinout Table 3 9 RS232 Pinout Signal Name Pin No BANK Description I O Level UART_TXD 19 3 Serial data Sends from FPGA 1 8V UART_RXD 20 3 Serial data Sends to FPGA 1 8V ...

Page 27: ...oltage needs to be set as 2 5V via changing J9 jumper position when Bank1 differential pairs serve as LVDS Bank voltage needs to be set as 1 2V via changing J9 jumper position when Bank0 differential pairs serve as MIPI I 6 Carefully use the Secure Mode of one time programming for product delivery During factory debugging it is recommended not to use the Secure Mode of one time programming and the...

Page 28: ...5 Gowin Software DBUG388 1 1E 21 21 5 Gowin Software Please refer to SUG100 Gowin Software User Guide for details ...

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