3 Development Board Circuit
3.5 LED
DBUG378-1.0E
16(25)
3.4.2
Clock, Reset Circuit
Figure 3-3 Clock, Reset
M19
AA22
KEY1
27MHz
ADM811
3.3V
F_RST_N
F_CLK
U1
U2
GW2A-
LV55PG484
3.4.3
Pinout
Table 3-3 FPGA Clock and Reset Pinout
Name
Pin No. BANK
Description
I/O Level
F_CLK
M19
2
27MHz crystal oscillator input
3.3V
F_RST_N
AA22
3
Reset Signal, active-low
3.3V
3.5
LED
3.5.1
Overview
There are six LEDs on the development board and users can display
the required status.
You can test the LEDs in the following ways:
When the FPGA corresponding pin output signal is logic low , the
LED is lit;
If the signal is high, LED is off.
