Chipset Features Setup
ROM P CI/I SA B IOS (2A 6LGT PU)
CHIPS ET F EATU RES SET UP
AWARD SOFTWARE, INC .
Bank 0/1 DRAM Timing
:
Normal-
Bank 2/3 DRAM Timing
:
Norma l
Bank 4/5 DRAM Timing
:
Norma l
SDRAM Cyc le L eng th
:
3
DRA M Cl ock
:
HCLK-33M
Mem or y Ho le
:
Disabled
Read A rrou nd wr ite
:
Disabled
Concu rren t PCI /Ho st
:
Disabled
Syste m BIO S Ca chea ble
:
Disabled
Video BIOS Cac heable
:
Disabled
Video RAM Cacheabl e
:
Disabled
AGP Aperture Size (MB )
:
64
AGP 2X MODE
:
Enable d
Auto Detect DIMM/PCI Clk :
Ena bled
Sprea d sp ectr um
:
Disabled
CPU H ost/ PCI Clo ck
:
Default
CPU W arni ng T emp erat ure :
Disabled
Curre nt C PU T emp erat ure :
36
°
C/96
°
F
Current System Temp .
:
26
°
C/78
°
F
Current CPUFAN Spee d
:
3825 RPM
Curre nt C HASF AN Spee d
:
0 RP M
Curre nt V
C C
( V)
:
4 .99
Curre nt V
I O
( V)
:
3 .49
Curre nt 12V
:
12.26
Curre nt V
C O R E
( V)
:
1 .65
Esc: Quit
- ¯ ® ¬
: S e l e c t I t e m
F1 : Help
PU/PD/+/- : Modify
F5 : Old Values (Shift)F2: Color
F6 : Load BIOS Default s
F7 : Load Setup Default s
Bank x/x DRAM Timing
Bank 0/1, 2/3, 4/5 DRAM Timing, DRAM timing is controlled by the DRAM timing
registers. The timings programmed into this register are dependent on the
system design. The slower timing may be required in certain system designs
to support loose layouts or slower memory. Options are SDRAM 10ns,
SDRAM 8ns, Normal, Medium, Fast, Turbo.
SDRAM Cycle Length
This feature is similar to SDRAM CAS Latency Time. It controls the time delay
(in clock cycles - CLKs) that passes before the SDRAM starts to carry out a
read command after receiving it. This also determines the number of CLKs for
the completion of the first part of a burst transfer. Thus, the lower the cycle
length, the faster the transaction. However, some SDRAM cannot handle the
lower cycle length and may become unstable. So, set the SDRAM Cycle
Length to
2
for optimal performance if possible but increase it to
3
if your
system becomes unstable. Cycle length specifications are to be found on
your SDRAM used in the system
DRAM Clock : HCLK-33M
This item allows you to set the DRAM Clock. Options are Host CLK or HCLK-
33M. You must set DRAM Clock as 66MHz if EDO RAM was installed on
board. Please set the item according to the Host (CPU) Clock and DRAM
Clock.
40
3303955 User's Manual
Summary of Contents for 3303955
Page 1: ...User s Manual Single Board Computer 3303955 Version 1 1 June 2001 ...
Page 10: ...Board Layout Front VT82C596B S o u th b rid g e 1 4 3 1 8 6 3303955 User s Manual ...
Page 36: ...This page was intentionally left blank 32 3303955 User s Manual ...
Page 47: ...This page was intentionally left blank 3303955 User s Manual 43 ...
