GD32W51x User Manual
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the same time. Only the device(s) which pulled SMBALERT# low will acknowledge the Alert
Response Address. When SMBHAEN is 0, it is configured as a slave device, the SMBA pin
is pulled low by setting the SMBALTEN bit in the I2C_CTL0 register. Meanwhile the Alert
Response Address is enabled. When SMBHAEN is 1, it is configured as a host, and the
SMBALTEN is 1, as soon as a falling edge is detected on the SMBA pin, the SMBALT flag is
set in the I2C_STAT register. If the ERRIE bit is set in the I2C_CTL0 register, an interrupt will
be generated. When SMBALTEN is 0, the ALERT line is considered high even if the external
SMBA pin is low. The SMBA pin can be used as a standard GPIO if SMBALTEN is 0.
Bus idle detection
If the master detects that the high level duration of the clock and data signals is greater than
t
HIGH,MAX
, the bus can be considered idle.
This timing parameter includes the case of a master that has been dynamically added to the
bus and may not have detected a state transition on a SMBCLK or SMBDAT lines. In this
case, in order to ensure that there is no ongoing transmission, the master must wait long
enough. The peripheral supports hardware bus idle detection.
The BUSTOA[11:0] bits must be programmed with the timer reload value to enable the t
IDLE
check in order to obtain the t
IDLE
parameter. To detect SCL and SDA high level timeouts, the
TOIDLE bit must be set. Then set TOEN in the I2C_TIMEOUT register to enable the timer. If
the high level time of both SCL and SDA is greater than ( 1) x 4 x t
I2CCLK
, the
TIMEOUT flag is set in the I2C_STAT register.
Note:
After the TOEN bit is set, the BUSTOA[11:0] bit and the TOIDLE bit cannot be changed.
SMBus slave mode
The SMBus receiver must be able to NACK each command or data it receives. For ACK
control in slave mode, slave byte control mode can be enabled by setting SBCTL bit in
I2C_CTL0 register.
SMBus-specific addresses should be enabled when needed. The SMBus Device Default
address (0b1100 001) is enabled by setting the SMBDAEN bit in the I2C_CTL0 register. The
SMBus Host address (0b0001 000) is enabled by setting the SMBHAEN bit in the I2C_CTL0
register. The Alert Response Address (0b0001100) is enabled by setting the SMBALTEN bit
in the I2C_CTL0 register.
19.3.10.
SMBus mode
SMBus Master Transmitter and Slave Receiver
The PEC in SMBus master mode can be transmitted by setting the PECTRANS bit before
setting the START bit, and the number of bytes in the BYTENUM[7:0] field must be configured.
In this case, the total number of transmissions when TI interrupt occur is BYTENUM-1. So if