GD32VF103 User Manual
69
5.3.
Register definition
RCU base address: 0x4002 1000
5.3.1.
Control register (RCU_CTL)
Address offset: 0x00
Reset value: 0x0000 xx83 where x is undefined.
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
PLL2STB PLL2EN PLL1STB PLL1EN
PLLSTB
PLL
EN
Reserved
CKMEN
HXTALB
PS
HXTALST
B
HXTALE
N
r
rw
r
rw
r
rw
rw
rw
r
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IRC8MCALIB[7:0]
IRC8MADJ[4:0]
Reserved
IRC8MST
B
IRC8MEN
r
rw
r
rw
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value.
29
PLL2STB
PLL2 Clock Stabilization Flag
Set by hardware to indicate if the PLL2 output clock is stable and ready for use.
0: PLL2 is not stable
1: PLL2 is stable
28
PLL2EN
PLL2 enable
Set and reset by software. Reset by hardware when entering Deep-sleep or Standby
mode.
0: PLL2 is switched off
1: PLL2 is switched on
27
PLL1STB
PLL1 Clock Stabilization Flag
Set by hardware to indicate if the PLL1 output clock is stable and ready for use.
0: PLL1 is not stable
1: PLL1 is stable
26
PLL1EN
PLL1 enable
Set and reset by software. Reset by hardware when entering Deep-sleep or Standby
mode.
0: PLL1 is switched off
1: PLL1 is switched on
25
PLLSTB
PLL Clock Stabilization Flag