GD32F20x User Manual
862
When DPSL value equals zero, the descriptor table is taken as contiguous by the
DMA, in ring mode
1
DAB
DMA arbitration bit
This bit indicates the arbitration mode between RxDMA and TxDMA.
0: Round-robin mode and DMA access priority is given in RTPR
1: Fixed mode. RxDMA has higher priority than TxDMA
0
SWR
Software reset bit
This bit can reset all core internal registers located in CLK_TX and CLK_RX.
It is cleared by hardware when the reset operation is complete in all clock domains.
Note:
Application must make sure this bit is 0 before writing any MAC core registers.
0: Core and inner register are not in reset state
1: Reset all core internal registers
27.4.43.
DMA transmit poll enable register (ENET_DMA_TPEN)
Address offset: 0x1004
Reset value: 0x0000 0000
This register is used by the application to make the TxDMA controller poll the transmit
descriptor table. The TxDMA controller can go into suspend state because of an underflow
error in a transmitted frame or the descriptor unavailable (DAV=0). Application can write any
value into this register for attempting to re-fetch the current descriptor.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TPE[31:16]
rw_wt
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TPE[15:0]
rw_wt
Bits
Fields
Descriptions
31:0
TPE[31:0]
Transmit poll enable bits
Writing to this register with any value makes DMA read the current descriptor
address which is indicated in ENET_DMA_CTDADDR register. If the fetched current
descriptor is available (DAV=1), DMA exits suspend state and resumes working. If
the fetched current descriptor is unavailable (DAV=0), the DMA returns to suspend
state again and the TBU bit in ENET_DMA_STAT register will be set.
27.4.44.
DMA receive poll enable register (ENET_DMA_RPEN)
Address offset: 0x1008
Reset value: 0x0000 0000
This register is used by the application to make the RxDMA controller poll the receive
Summary of Contents for GD32F20 Series
Page 191: ...GD32F20x User Manual 191 Bits Fields Descriptions 31 0 TRNDATA 31 0 32 Bit Random data ...
Page 290: ...GD32F20x User Manual 290 conversion is ongoing ...
Page 325: ...GD32F20x User Manual 325 15 0 ALRM 15 0 RTC alarm value low ...
Page 385: ...GD32F20x User Manual 385 ...
Page 523: ...GD32F20x User Manual 523 clears AERR bit by writing 0 to it ...