GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
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Figure 25-32. Burst write operation
Chip Enable
(EXMC_SDNEx)
Column Address
Strobe
(EXMC_NCAS)
Row Address
Strobe
(EXMC_NRAS)
Write Enable
(EXMC_SDNWE)
Data
(EXMC_D[31:0])
Clock
(EXMC_SDCLK)
Address
(EXMC_A[12:0])
Col
m
Col
m+1
bank
a
Col
m+3
Col
m+4
Col
m+2
RCD = 3
Active Row
Write
Command
Row
n
Bank Address
(EXMC_A[15:14])
Col
m+5
Col
m+6
Col
m+8
Col
m+9
Col
m+7
Col
m+10
bank
a
Col
m
Col
m+1
Col
m+3
Col
m+4
Col
m+2
Col
m+5
Col
m+6
Col
m+8
Col
m+9
Col
m+7
Col
m+10
The RW split module accepts AHB commands, and transfers them to single read/write
accesses on the SDRAM memory according to the ratio of the data width between the AHB
bus and the SDRAM memory interface.
Inside the RW split module, there are two write FIFOs, which buffers the data and address of
the AHB write commands. When neither of the write FIFOs is empty, write access occurs.
When the BRSTRD bit of EXMC_SDCTL0 register is set, the RW split module can anticipate
the next read access. The read FIFOs are used to store data read in advance during the CAS
latency period (configured by the CL bits of EXMC_SDCTLx) and during the PIPED delay
(configured by the PIPED bits of EXMC_SDCTL0).
The RDATA FIFO can buffers up to 6 32-bit read data words, while the RADDR FIFO carries
6 14-bit read address tags to identify each of them. Every address tag is comprised of 11 bits
for the column address, 2 bits for the internal bank address and 1 bit to select the SDRAM
memories.
When there is an read commands on the AHB bus, the RW split module will firstly checks
whether the address matches one of the address tags, and data are directly read from the
FIFO when it is true. Otherwise, a new read command is issued to the memory and the FIFO
is updated with new data. If the FIFO is full, the older data are lost.
Figure 25-33. Read access when FIFO not hit (BRSTRD=1, CL=2, SDCLK=2, PIPED=2)
and Figure 25-34. Read access when FIFO hit (BRSTRD=1) specify the Read FIFO
operation.