GigaDevice Semiconductor GD32F20 Series, User Manual

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GD32F20x User Manual
692
Figure 25-9. Mode A read access
Address
(EXMC_A[25:0])
Byte Lane Select
(EXMC_NBL[1:0])
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Memory Output
Address Setup Time
(ASET HCLK)
Data Setup Time
(DSET HCLK)
Figure 25-10. Mode A write access
Address
(EXMC_A[25:0])
Byte Lane Select
(EXMC_NBL[1:0])
Chip Enable
(EXMC_NEx)
Output Enable
(EXMC_NOE)
Write Enable
(EXMC_NWE)
Data
(EXMC_D[15:0])
Address Setup Time
(ASET HCLK)
Data Setup Time
(DSET HCLK)
EXMC Output
1 HCLK
The different between mode A and mode 1 write timing is that read/write timing is specified
by the same set of timing configuration, while mode A write timing configuration is
independent of its read configuration.
Table 25-9. Mode A related registers configuration
EXMC_SNCTLx
Bit Position Bit Name Reference Setting Value
31-20 Reserved 0x000
19 SYNCWR 0x0
18-16 Reserved 0x0
15 ASYNCWTEN Depends on memory
14 EXMODEN 0x1
13 NRWTEN 0x0
12 WEN Depends on user
11 NRWTCFG No effect
10 WRAPEN 0x0
9 NRWTPOL Meaningful only when the bit 15 is set to 1