GigaDevice Semiconductor GD32F10 Series, User Manual

Page: 664 / 853

GD32F10x User Manual
664
It is active when either transmit or receive medium is in non idle state. The PHY must ensure
that the MII_CRS signal remains asserted throughout the duration of a collision condition.
This signal is not required to transition synchronously with respect to the TX and RX clock.
- MII_COL : Collision detection signal, only working in Half-duplex mode, controlled by the
PHY. It is active when a collision on the medium is detected and must it will remain active
while the collision condition continues. This signal is not required to transition synchronously
with respect to the TX and RX clock.
- MII_RXD[3:0] : Receive data line, each 4 bit data transfer; data are valid when the
MII_RX_DV signal is effective. MII_RXD[0] is the least significant bit and MII_RXD[3] is the
most significant bit. While MII_RX_DV is de-asserted and MII_RX_ER is asserted, a specific
MII_RXD[3:0] value is used to indicate specific information (see
Table 22-3. Rx interface
signal encoding
).
- MII_RX_DV : Receive data valid signal, controlled by the PHY. It is asserted when PHY is
presenting data on the MII for reception. It must be asserted synchronously with the first 4-bit
of the frame and must remain asserted while all bits to be transmitted are presented on the
MII. It must be de-asserted prior to the first clock cycle that follows the final 4-bit. In order to
receive the frame correctly, the effective signal starting no later than the SFD field.
- MII_RX_ER : Receive error signal. It must be asserted for one or more RX clock to indicate
MAC detected an error in the receiving process. The specific error reason needs to cooperate
with the state of the MII_RX_DV and the MII_RXD[3:0] data value (see
Table 22-3. Rx
interface signal encoding
).
Table 22-3. Rx interface signal encoding
MII_RX_ER MII_RX_DV MII_RXD[3:0] Description
0 0 0000 to 1111 Normal inter-frame
0 1 0000 to 1111 Normal reception frame data
1 0 0000 Normal inter-frame
1 0 0001 to 1101 Reserved
1 0 1110 False carrier indication
1 0 1111 Reserved
1 1 0000 to 1111 Data reception with errors
MII clock sources
To generate both TX_CLK and RX_CLK clock signals, the external PHY needs an external
25MHz clock. This 25MHz clock does not require the same one with MAC clock. It can use
the external 25MHz crystal or the
output clock of microcontroller’s CK_OUT0 pin. If the clock
source is selected from CK_OUT0 pin, the MCU needs to configure the appropriate PLL to
ensure the output frequency of CK_OUT0 pin is 25MHz.