GD32E23x User Manual
360
Insertion dead time for complementary PWM
The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN
is also necessary. The field named DTCFG defines the dead time delay that can be used for
channel 0. The detail about the delay time, refer to the register TIMERx_CCHP.
The dead time delay insertion ensures that no two complementary signals drive the active
state at the same time.
When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled
because under PWM0 mode. At point A in the
Figure 14-64. Complementary output with
CHx_O signal remains at the low value until the end of the deadtime
delay, while CHx_ON will be cleared at once. Similarly, At point B when counter match
(counter = CHxVAL) occurs again, OxCPRE is cleared, CHx_O signal will be cleared at once,
while CHx_ON signal remains at the low value until the end of the dead time delay.
Sometimes, we can see corner cases about the dead time insertion. For example:
The dead time delay is greater than or equal to the CHx_O duty cycle, then the CHx_O
signal is always the inactive value. (as show in the
Figure 14-64. Complementary output
The dead time delay is greater than or equal to the CHx_ON duty cycle, then the CHx_ON
signal is always the inactive value.
Figure 14-64. Complementary output with dead-time insertion.
0
CHxVAL
CAR
CxOPRE
CHx_O
CHx_ON
Deadtime
Corner case Deadtime > pulse width
CHx_O
CHx_ON
Deadtime
Pulse width
Deadtime
A
B
Break mode
In this mode, the output CHx_O and CHx_ON are controlled by the POEN, IOS and ROS bits
in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and
