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Hardware Installation Process
Introduce RIMM (Rambus In-line Memory Module)
Direct Rambus Memory Controller
Directly support a Dual Direct Rambus * Channel
Supports 300&400 MHz Direct Rambus * Channel @ 100MHz host bus frequency.
Maximum memory array size up to 256MB using 64Mb/72Mb, 512MB using 128Mb/144Mb,
1GB using 256Mb/288Mb DRAM technology
Supports up to 32 Direct Rambus devices per channel
Supports a maximum DRAM address decode space of 4GB
Configurable optional ECC operation
ECC with single bit Error Correction and multiple bit Error Detection
Single bit errors corrected and written back to memory (auto-scrubbing)
Parity mode not supported
APIC memory space in hardware. It is the BIOS or system designer's responsibility to limit DRAM
population so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated.
Direct RDROM
SPD ROM
Direct Rambus
Clock Generator
(DRCG)
Rambus Channel
Master Device
Direct Rambus ASIC Cell(RAC)
RIMM Module
RIMM Module
RIMM
Continuity
Module
RIMM Continuity
Module
RIMM
Connector