Giga-tronics 80350A, Operation & Maintenance Manual

Page: 36 / 110

Series 8035XA Peak Power Sensors
2-12 Manual 21568, Rev. F, March 2008
2.3.7 Sample Delay Offset
In addition to compensating for delay line triggering variations or external triggering cables,
sample delay offset can be used to set a 0.0 ns time reference point after the trigger point (see
Figure 2-13).
Figure 2-13: Sample Delay
total = sample delay + sample delay offset
total = 20,000 s + 0.120 s = 200 120 s
µ µ µ
total = 200,000 s + (-0.010 s) = 199.990 s
µ µ µ
t
t
t
or
total
t
The use of a digital oscilloscope can permit better viewing of data. There are two small markers
injected onto this waveform. The first is a small triggering marker which is added slightly after
the trigger point. The second marker on the waveform is the sample marker. The sample
marker is located slightly behind the actual sample point. There may be small markers at the
end of the sample transfer and when the trigger signal occurs. Because the visibility of these
markers varies greatly with signal level and horizontal sweep rate, the use of the SAMPLE
DELAY output is recommended.
In Figure 2-14, triggering occurs at the frame start of a pulsed TDMA communications signal.
The trigger level is set such that triggering can only occur on the highest amplitude pulse; this
provides stable triggering. A sample delay offset is used to set a 0.0 ns reference point at the
start of the third data burst pulse.
Figure 2-14: Using SD to Offset a 0 ns Time Reference
Detector Out
Connection
Sample Delay Offset
Sample
Delay
Sample
Delay
Internal
Trigger
Level
Sample Delay
Connection