Spare Time Gizmos
SBC6120 User's Manual
03/09/2003 1:35 PM
Page 14
or nothing. The maximum capacity of the RAM disk array is thus 2Mb - a respectably sized disk
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for OS/8.
Figure 4 - RAM disk daughter board
The SBC6120 maps these RAM chips into panel memory via the memory decode GAL and, when
memory map 3 (see 3.2) is enabled, all indirect references to panel memory will access the RAM
disk array. Since the RAM disk is only a byte wide, write operations discard the upper four bits of
a twelve bit word, and when reading these bits are undefined and should be masked off by the
software.
Addressing the RAM disk is a little tricky, since a 2Mb memory requires a total of 21 address bits
- quite a bit more than a PDP-8 can manage. RAM disk address bits 0..11 (the low order bits,
contrary to the PDP-8 convention) are supplied by the HD-6120 MA11-0. The remaining 7 bits
needed by each 512K SRAM come from a special register, the
D
isk
A
ddress
R
egister, which can
be loaded via the
LDAR
IOT. The final two bits needed by the DS1221 to select one of the four
SRAM chips come from the HD-6120
EMA0
and
EMA1
(
EMA2
is not used at the moment).
Put more simply, the data field selects the SRAM chip used, the DAR selects the 4K byte "bank"
within the chip, and the normal memory address selects the individual byte within the bank.
IOT
Function
LDAR
6410
Load RAM disk address register
Table 8 - RAM Disk IOTs
3.5 IDE I
NTERFACE
In the SBC6120 the IDE interface is implemented by a standard 8255 PPI, which gives us 24 bits
of general purpose parallel I/O. PPI port A is connected the high byte (DD8..DD15) of the IDE
data bus and port B is connected to the low byte (DD0..DD7). Port C supplies IDE control signals
according to the following table.
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Almost as big as a RK05J!
