VRC2000
Installation and Operations Manual Page 103
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Each of the building blocks will be discussed in the following text. During this
discussion, refer to the electrical diagrams in Appendix J: Schematics (Page 129).
Microcontroller Theory
The VRC2000’s central processing unit (CPU) is a MC146805E2 controller.
It has external and timer interrupts, and it consumes very little power. The
MC146805 accesses 8K of memory but, by address decoding, the unit is able
support additional ROM/RAM to allow for addressing the digital voice
synthesizer’s word library.
The chip-enable logic used in the VRC2000 is outlined in Table 19
(below).
The SPCCMDWR* enables the MM54104 digital voice synthesizer when
active, and the SPCADRWR* controls the address selection of which word
ROM the digital voice synthesizer is accessing. The ADCMDWR* enables
the demultiplexer used on the metering channel inputs while the
ADDTHRD* and the ADDTLRD* lines control which data byte is accessed.
The four CMDxxxxx* enable lines each control eight command-channel
switches configured in four channels of two switches each. CMDDTAWR*
controls command channels 1–4’s switch functions (*, #); CMDDTBWR*
controls command channels 5–8’s switch functions, and so on. The status
channel enable lines STSDTARD* and STSDTBRD* each control half of the
16 status-channel inputs.
The microprocessor master clock runs at 4MHz. The 256Hz pulses that U25
(a MC146818 clock) generates are critical to the interrupt service routines.
U29 (a 74HC541 tristate input port) decodes the VRC2000’s eight hardware
interrupts. These interrupts are prioritized as outlined in Table 20 (next page,
top).
Table 19. VRC2000 Chip-Enable Logic
Identity
Function
Destination
IOEN* Modem Data Interface
SPCCMDWR* Speech Command Write U6 74HC574 Clock
SPCADRWR* Speech Address Write U5 74HC574 Clock
ADCMDWR* A/D Command Write U38 74HC574 Clock
CMDDTDWR* Command Data D Write U53 74HC574 Clock
CMDDTCWR* Command Data C Write U51 74HC574 Clock
CMDDTBWR* Command Data B Write U49 74HC574 Clock
CMDDTAWR* Command Data A Write U47 74HC574 Clock
ADDTHRD* A/D Data High Byte Read U37 AD573 HBE*
ADDTLRD* A/D Data Low Byte Read U37 AD573 LBE*
STSDTARD* Status Data A Read U39 74HCT541 G1*, G2*
STSDTBRD* Status Data B Read U40 74HCT541 G1*, G2*
* Denotes Active Low Input