Genesys GL3520 Design Manual Download Page 21 | Manualshive

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Genesys GL3520 Design Manual Download Page 21

USB 3.0 Hub Design Guide

© 2015 Genesys Logic, Inc. - All rights reserved.

Page 21

GLI Confidential

Figure 2.22

Bottom Layer:

1.2V power source to USB3.0 HUB

L1 Inductance

Top Layer: Minimum 2 via hole

Top layer Color

Bottom layer Color

Bottom Layer:

5V power source

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Summary of Contents for GL3520

Page 1: ...USB 3 0 Hub Controller Design Guide Revision 2 11 Jan 06 2015 Genesys Logic Inc...

Page 2: ...ety rights No license is granted hereunder Disclaimer All Materials are provided as is Genesys Logic Inc makes no warranties express implied or otherwise regarding their accuracy merchantability fitne...

Page 3: ...8 Modify Ch4 The Example of Differential Traces and Impedance p 18 1 50 04 22 2011 Add Ch6 ESD Protection p 22 1 60 05 18 2011 Add Figure 5 4 Hub Trace on Mother Board p 22 1 70 05 19 2011 Update 3 2...

Page 4: ...ines 7 2 3 4 Trace Bend 8 2 3 5 Reference Plane 8 2 3 6 Signal Return Path 9 2 3 7 Differential Pair Layout 11 2 3 8 Avoid Stub on Differential Traces 12 2 3 9 SS Trace Swap 12 2 4 Circuit and Compone...

Page 5: ...Page 5 GLI Confidential 3 SYSTEM DESIGN GUIDELINES 22 3 1 System Design Overview 22 3 2 Channel Description with a Cable 23 3 3 Channel Description without a Cable 24 3 4 Hub Trace on Mother Board 25...

Page 6: ...INES 2 1 AC Coupling Capacitors PHY is a component where the transmitter and receiver are located and operated together The AC coupling capacitors are associated with the transmitter Differential Pair...

Page 7: ...ial Pairs Trace 2 3 1 Differential Pair Impedance The differential impedance requirement must be 90 Ohm 10 and trace width spacing may be different by PCB material characteristic base on PCB Vendor su...

Page 8: ...135 degrees 135 and the length of B and C should be minimized Pad Pad A C B Figure 2 2 2 3 5 Reference Plane Make sure that the differential trace layer and adjacent layer are with solid GND plane The...

Page 9: ...e a trace so that it straddles a plane split See Fig 2 4 Power Plane Ground Island L3 Vcc layer Differential pair at Bottom layer Signal Via Place Stitching Vias close to Signal Via Space within 50 mi...

Page 10: ...be routed over a split plane as the return path is not able to follow the signal trace If a plane is split between a sink and source route the signal trace around it If the forward and return paths o...

Page 11: ...and also be kept as symmetric as possible as shown in Fig 2 7 Bad Layout Non symmetric Preferred Layout symmetric routing Figure 2 7 When vias are used they should always be placed in same location an...

Page 12: ...own in Fig 2 10 Pin TXN of the IC can be connected to TXP of the connector Pin TXP of the IC can be connected to TXN of the connector Pin RXN of the IC can be connected to RXP of the connector Pin RXP...

Page 13: ...USB 3 0 Hub Design Guide 2015 Genesys Logic Inc All rights reserved Page 13 GLI Confidential Figure 2 11...

Page 14: ...f decoupling capacitor positioning on top layer An example of decoupling capacitor positioning on Bottom layer 2 4 2 RTERM Resistor RTERM reference resistor use 680 ohm 1 and place as close to the IC...

Page 15: ...tors and the resistor as close as possible to the IC Recommend less than 1cm if possible And the resistor need be between the IC and the capacitor See Fig 2 12 Figure 2 12 3 Do not route X1 and X2 und...

Page 16: ...n small area Keep analog components away from LX node to prevent stray capacitive noise pick up 4 Keep the connect feedback network behind the output capacitors Place the feedback components near the...

Page 17: ...for fast charging For example if the design supports four charging downstream ports the 5V power supply must be capable of delivering total 6Amps 2 7 Thermal Reduction Optimum layout suggestion for t...

Page 18: ...al signal trace Gap 20 mils or use GND plane isolate The GND plane and differential signal trace Gap 20 mils 2 8 2 USB 2 0 The GND of the signal lines shall have spacing of at least 20mil with the sig...

Page 19: ...is large current passing though the pin 2 of UP1722PDE6 This pin has to be connected with the ground of CIN and COUT and the trace has to be wide Increase the amount of via holes at the ground of pin...

Page 20: ...hould be connected to inductor by wide and short trace and keep sensitive components away from this trace There is large current passing though the pin 88 GND of GL3521 This pin has to be connected wi...

Page 21: ...5 Genesys Logic Inc All rights reserved Page 21 GLI Confidential Figure 2 22 Bottom Layer 1 2V power source to USB3 0 HUB L1 Inductance Top Layer Minimum 2 via hole Top layer Color Bottom layer Color...

Page 22: ...channel loss and reflection effect of Device or Upstream port of HUB The figure below shows the compliance channel designs for hosts devices and cables The host and cable compliance channels are used...

Page 23: ...ble The insertion loss of 8 7 8 FR4 trace is around 0 296dB per inch 2 5G signal PCB trace w o via The insertion loss of 34AWG cable is around 4 4dB per meter So the worst case of total insertion loss...

Page 24: ...oss of 8 7 8 FR4 trace is around 0 296dB per inch 2 5G signal PCB trace w o via Based on the previous case description the max insertion loss is 20dB including PCB trace PCB via and connector However...

Page 25: ...25 GLI Confidential 3 4 Hub Trace on Mother Board Figure 3 4 Hub Upstream Port Connected to Host Fig 3 4 The recommended length of Hub trace is up to 9 inch on the mother board However if the Host tr...

Page 26: ...IC to provide better ESD protection as shown in Fig 4 1 Figure 4 1 4 2 Hub with External Charger IC Fig 4 2 shows the suggested layout guide if the external charger IC is implemented for battery charg...

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