Embedded PC/RTOS Features 39
3.4 Watchdog Timer
The
VMIVME
‐
7807/VME
‐
7807RC
provide
a
programmable
Watchdog
Timer
(WDT)
which
can
be
used
to
reset
the
system
if
software
integrity
fails.
3.4.1 WDT Control Status Register (WCSR)
The
WDT
is
controlled
and
monitored
by
the
WDT
Control
Status
Register
(WCSR)
which
is
located
at
offset
0x08
from
the
address
in
BAR2.
The
mapping
of
the
bits
in
this
register
is
shown
in
The
“WDT
Timeout
Select”
field
is
used
to
select
the
timeout
value
of
the
WDT
as
shown
in
The
“SERR/RST
Select”
bit
is
used
to
select
whether
the
WDT
generates
an
SERR#
on
the
local
PCI
bus
or
a
system
reset.
If
this
bit
is
set
to
“0”,
the
WDT
will
generate
a
system
reset.
Otherwise,
the
WDT
will
make
the
local
PCI
bus
SERR#
signal
active.
The
“WDT
Enable”
bit
is
used
to
enable
the
Watchdog
Timer
function.
This
bit
must
be
set
to
“1”
in
order
for
the
Watchdog
Timer
to
function.
Note
that
since
all
registers
default
to
zero
after
reset,
the
Watchdog
Timer
is
always
disabled
after
a
reset.
The
Watchdog
Timer
must
be
re
‐
enabled
by
the
application
software
after
reset
in
order
for
the
Watchdog
Timer
to
continue
to
operate.
Once
the
Watchdog
Timer
is
enabled,
the
application
software
must
refresh
the
Watchdog
Timer
within
the
selected
timeout
period
to
prevent
a
reset
or
SERR#
from
being
generated.
The
Watchdog
Timer
is
refreshed
by
performing
a
write
to
the
WDT
Keepalive
register
(WKPA).
The
data
written
is
irrelevant.
Table 3-11 WCSR Bit Mapping
Field
Bits
Read or Write
SERR/RST Select
WCSR[16]
R/W
WDT Timeout Select
WCSR[10..8]
R/W
WDT Enable
WCSR[0]
R/W
All of these bits default to “0” after system reset. All other bits are reserved.
Table 3-12 Selecting Timeout Value of the WDT
Timeout
WCSR[10]
WCSR[9]
WCSR[8]
135 s
0
0
0
33.6 s
0
0
1
2.1 s
0
1
0
524 ms
0
1
1
262 ms
1
0
0
131 ms
1
0
1
32.768 ms
1
1
0
2.048 ms
1
1
1
