Embedded PC/RTOS Features 35
Each
timer
can
be
independently
enabled
by
writing
a
“1”
to
the
appropriate
“Timer
x
Enable”
field.
Similarly,
the
generation
of
interrupts
by
each
timer
can
be
independently
enabled
by
writing
a
“1”
to
the
appropriate
“Timer
x
IRQ
Enable”
field.
If
an
interrupt
is
generated
by
a
timer,
the
source
of
the
interrupt
may
be
determined
by
reading
the
“Timer
x
Caused
IRQ”
fields.
If
the
field
is
set
to
“1”,
then
the
respective
timer
caused
the
interrupt.
Note
that
multiple
timers
can
cause
a
single
interrupt.
Therefore,
the
status
of
all
timers
must
be
read
to
ensure
that
all
interrupt
sources
are
recognized.
A
particular
timer
interrupt
can
be
cleared
by
writing
a
“0”
to
the
appropriate
“Timer
x
Caused
IRQ”
field.
Alternately,
a
write
to
the
appropriate
Timer
x
IRQ
Clear
(TxIC)
register
will
also
clear
the
interrupt.
When
clearing
the
interrupt
using
the
“Timer
x
Caused
IRQ”
fields,
note
that
it
is
very
important
to
ensure
that
a
proper
bit
mask
is
used
so
that
other
register
settings
are
not
affected.
The
preferred
method
for
clearing
interrupts
is
to
use
the
“Timer
x
IRQ
Clear”
registers
described
on
3.3.2 Timer Control Status Register 2 (TCSR2)
The
timers
are
also
controlled
by
bits
in
the
Timer
Control
Status
Register
2
(TCSR2)
located
at
offset
0x04
from
the
address
in
BAR2.
The
mapping
of
the
bits
in
this
register
is
shown
in
The
“Read
Latch
Select”
bit
is
used
to
select
the
latching
mode
of
the
programmable
timers.
If
this
bit
is
set
to
“0”,
then
each
timer
output
is
latched
upon
a
read
of
any
one
of
its
addresses.
For
example,
a
read
to
the
TMRCCR12
register
latches
the
count
of
timers
1
and
2.
A
read
to
the
TMRCCR3
register
latches
the
count
of
timer
3.
This
continues
for
every
read
to
any
one
of
these
registers.
As
a
result,
it
is
not
possible
to
capture
the
values
of
all
four
timers
at
a
given
instance
in
time.
However,
by
setting
this
bit
to
“1”,
all
four
timer
outputs
will
be
latched
only
on
reads
to
the
Timer
1
&
2
Current
Count
Register
(TMRCCR12).
Therefore,
to
capture
the
current
count
of
all
four
timers
at
the
same
time,
perform
a
read
to
the
TMRCCR12
first
(with
a
32
‐
bit
read),
followed
by
a
read
to
TMRCCR3
and
TMRCCR4.
The
first
read
(to
the
TMRCCR12
register)
causes
all
four
timer
values
to
be
latched
at
the
same
time.
The
subsequent
reads
to
the
TMRCCR3
and
TMRCCR4
registers
do
not
latch
new
count
values,
allowing
the
count
of
all
timers
at
the
same
instance
in
time
to
be
obtained.
3.3.3 Timer 1 & 2 Load Count Register (TMRLCR12)
Timers
1
&
2
are
16
‐
bits
wide
and
obtain
their
load
count
from
the
Timer
1
&
2
Load
Count
Register
(TMRLCR12),
located
at
offset
0x10
from
the
address
in
BAR2.
The
mapping
of
bits
in
this
register
is
shown
in
Table 3-4 TCSR2 Bit Mapping
Field
Bits
Read or Write
Read Latch Select
TCSR2[0]
R/W
Reserved
All Other Bits
R/W
All of these bits default to “0” after system reset.
