GE Mini COM Express 10, Hardware Reference Manual

Page: 51 / 82

6.4 Supervision Configuration Registers
Supervision Configuration Registers
Index Name
Description
0x30 Control
Logical device activation control
0x60
Supervision
Base (High)
Supervision registers base I/O address (upper 8 bits)
0x61
Supervision
Base (Low)
Supervision registers base I/O address (lower 8 bits)
6.4.1 Supervision Control
The Supervision Control register allows the logical device to be activated or deactivated.
Supervision Control Register (LDN 0x0A, Index 0x30)
Bit Name Access Default
Description
7:01
—
R 0b0000000 Reserved
0 ACTIVATE R/W 0
Logical device activation
0: Disabled
1: Enabled
6.4.2 Supervision Base Address
The Supervision Base Address register sets the I/O base address for the supervision
registers. The base address must be aligned on an 8-byte boundary.
Supervision Base Address Register (LDN 0x0A, Index 0x60-0x61)
Bit Name Access Default
Description
15:03
ADDR[15:3]
R/W 0x0000 Base address bits 15:03
2
—
R 0b000 Reserved
FPGA Registers GFK-2896 Hardware Reference Manual 51
For public disclosure