5.1.2
JTAG Connector
A 23-pin 0.3 mm (0.01 in) pitch flexible printed circuit receptacle provides access to the
board JTAG chain to allow programming of the FPGA, processor debug access, and
manufacturing board test. The mating cable is Molex series 15015.
5.1.2.1
Pin Assignments
JTAG Pin Assignments
Pin #
Signal
1
GND
2
BOARD_SEL#
3
APU_SEL#
4
SMB_CLK
5
GND
6
DBREQ#
7
SMB_DAT
8
DBRDY
9
GND
10
TDI
11
DBG_RESET#
12
TMS
13
GND
14
+1.8V_STBY
15
GND
16
+1.8V_STBY
17
DBG_PWRBTN#
18
TDO
19
GND
20
TRST#
21
APU_RST#
22
TCK
23
GND
TCK
,
TMS
,
TDI
,
TDO
, and
TRST#
are the standard IEEE 1149.1 JTAG signals.
BOARD_SEL#
and
APU_SEL#
are used to control insertion and removal of certain devices
within the JTAG chain. Refer to the section,
DBRDY
,
DBREQ#
,
APU_RST#
,
DBG_PWRBTN#
, and
DBG_RESET#
are processor debug
signals.
SMB_CLK
and
SMB_DAT
are wired to SMBus 0, which connects to the memory SPD
EEPROM.
40
GFK-2896
Mini COM Express Type 10 Module mCOM10-L1500
For public disclosure
Summary of Contents for Mini COM Express 10
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