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GE mCOM10-L1500 Hardware Reference Manual Download Page 76

RTC

Battery-backed circuit in PC-AT systems that keeps system time and date as well

as certain system setup parameter

SDVO

Intel-defined format for digital video output used with carrier board conversion

ICs to create parallel, TMDS, and LVDS flat panel formats, as well as NTSC and PAL TV
outputs

SPD

Serial EEPROM associated with a bank of memory that contains the

characteristics and operating parameters of the memory

SPI

A four-wire (clock, data in, data out, and chip select) bus typically used for

low-speed non-volatile memories. Standard for a synchronous serial data bus with
Master-Slave devices.

TAP

JTAG boundary scan control port

UDIMM

Memory module where the address and control bus is directly connected to the

memory controller

76

Mini COM Express Type 10 Module mCOM10-L1500

For public disclosure

Summary of Contents for mCOM10-L1500

Page 1: ...GE Intelligent Platforms GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 Hardware Reference Manual For public disclosure ...

Page 2: ...e patents or pending patent applications covering subject matter in this document The furnishing of this document does not provide any license whatsoever to any of these patents GE provides the following document and the information included therein as is and without warranty of any kind expressed or implied including but not limited to any implied statutory warranty of merchantability or fitness ...

Page 3: ...eable Unit GPIO General Purpose Input Output GPU Graphics Processing Unit HDMI High Definition Multimedia Interface I2C Inter Integrated Circuit IEEE Institute of Electrical and Electronic Engineers JTAG Joint Test Access Group LAN Local Area Network LPC Low Pin Count LSB Least Significant Byte LVDS Low Voltage Differential Signaling MAC Media Access Control MDI Media Dependent Interface MSB Most ...

Page 4: ... Single Root I O Virtualization TAP Test Access Port TDP Thermal Design Power TPM Trusted Platform Module UART Universal Asynchronous Receiver Transmitter UDIMM Unbuffered DIMM UEFI Unified EFI UHCI Universal Host Controller Interface USB Universal Serial Bus VMDq Virtual Machine Device Queues WDT WatchDog Timer 4 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure ...

Page 5: ...result in personal injury or death Caution Indicates a procedure condition or statement that if not strictly observed could result in damage to or destruction of equipment Attention Indicates a procedure condition or statement that should be strictly followed to improve these applications For public disclosure ...

Page 6: ...rvice RMA returns and other functions World wide headquarters of GE Intelligent Platforms Inc GE Intelligent Platforms Inc 2500 Austin Drive Charlottesville VA 22911 U S A Regional Areas WW world wide EU Europe Russia Near East India Africa US Americas and Pacific Rim Japan Korea China Philippines AUS NZ Technical Support Free technical support is available by phone or email Telephone support is a...

Page 7: ...artup 22 3 4 1 UEFI Firmware Setup 22 4 System Architecture 23 4 1 G Series SoC Processor 23 4 1 1 Memory 24 4 1 2 Digital Display Interface 24 4 1 3 PCI Express 24 4 1 4 BIOS UEFI Firmware 25 4 1 5 Serial ATA 25 4 1 6 USB 25 4 1 7 Secure Digital or General purpose I O 25 4 1 8 Audio 25 4 1 9 Clocks 26 4 1 10 Real Time Clock and CMOS RAM 26 4 1 11 LPC Bus 26 4 1 12 SMBus 26 4 2 Gigabit Ethernet In...

Page 8: ...ation Registers 48 6 3 1 UART Control 48 6 3 2 UART Base Address 48 6 3 3 UART Interrupt Request 49 6 3 4 UART Mode 50 6 4 Supervision Configuration Registers 51 6 4 1 Supervision Control 51 6 4 2 Supervision Base Address 51 6 5 I2C Controller Configuration Registers 52 6 5 1 I2C Control 52 6 5 2 I2C Base Address 52 6 5 3 I2C IRQ 53 6 6 Watchdog Timer Configuration Registers 54 6 6 1 Watchdog Time...

Page 9: ...ers 65 6 8 1 Reset Cause 65 6 8 2 Last Reset 66 6 9 I2C Controller Run Time Registers 67 6 9 1 Clock Prescale 67 6 9 2 Control 68 6 9 3 Transmit 68 6 9 4 Receive 68 6 9 5 Command 69 6 9 6 Status 70 6 9 7 Watchdog Timer Run Time Registers 71 7 Specifications 73 Glossary of Terms 75 Index 77 GFK 2896 Hardware Reference Manual 9 For public disclosure ...

Page 10: ...Notes 10 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure ...

Page 11: ... ports eight USB 2 0 host interfaces two of which support USB 3 0 low voltage differential signaling LVDS flat panel or embedded DisplayPort plus a Digital Display Interface DDI LPC SPI SMBus I2C secure digital or general purpose I O and high definition audio ports to the module connector Refer to PICMG COM 0 R2 1 COM Express Module Base Specification located at www picmg org This document describ...

Page 12: ... lanes configurable as either 4 1 or 1 4 Eight MB SPI Flash for UEFI BIOS firmware Two SATA ports Eight USB 2 0 host interfaces two of which also support USB 3 0 SuperSpeed Two simultaneous display outputs LVDS eDP configurable and DDI LPC Bus One internal plus one external SPI bus SMBus I2C bus SDIO or GPIO configurable High definition Audio Two 16550 compatible serial ports Express Card support ...

Page 13: ...South Bridge LVDS eDP DDI0 VGA I210 PCIe PCIe 0 3 GbE0 DDR3L 2 4 8GB ECC 2x SATA 8x USB 2x USB_SS HDA GPIO SD Flash SMBus LPC FPGA UART I2C WDog UART Supv Ser0 Ser1 I2C WDT SPD Debug SPI EeeP SMBus User mCOM10 L1500 Functional Block Diagram Introduction GFK 2896 Hardware Reference Manual 13 For public disclosure ...

Page 14: ...Notes 14 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure ...

Page 15: ...ng or removing modules without observing this precaution could result in damage to this and or other modules in your system Wear a properly functioning anti static strap and make sure you are fully grounded Any surface upon which you place the unprotected module should be static safe which is usually facilitated by the use of anti static mats From the time the board is removed from the anti static...

Page 16: ...ng the board or module or fitting the device into your system read the manual carefully Also adhere to the following guidelines Observe all precautions for electrostatic sensitive modules If the product contains batteries do not place the board on conductive surfaces anti static plastic or sponge which can cause shocks and lead to battery or board trace damage Do not exceed the specified operation...

Page 17: ...tical to ensure proper operation and long term reliability When unpacking and handling the board be sure to hold the board as displayed in the following figure Board Handling Unpacking and Inspection GFK 2896 Hardware Reference Manual 17 For public disclosure ...

Page 18: ...Notes 18 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure ...

Page 19: ...he supply meets the voltage and total power requirements of the mCOM10 L1500 Warning Verify that the power supply is turned OFF while plugging or unplugging the board onto or from a carrier card respectively 3 1 2 Keyboard and Mouse The keyboard is attached to the carrier board A compatible keyboard for initial system operation on the carrier board is required Depending on your application this ma...

Page 20: ...ower and external supplies have been turned off Verify that the jumpers on the carrier board are correctly configured for your application Mount the board on the carrier board very carefully Refer to the procedure To install the mCOM10 L1500 onto the carrier board Do not restore power until all modules are fitted correctly and all connections have been made properly 20 GFK 2896 Mini COM Express Ty...

Page 21: ...nstall the mCOM10 L1500 onto the carrier board 1 Carefully slide the mCOM10 L1500 board onto the connector on the carrier board 2 Fasten the mCOM10 L1500 to the board using four M2 5 screws Tighten the screws with a torque of 0 6 N m 5 in lb Installing the mCOM10 L1500 onto the Carrier Card Installation and Startup GFK 2896 Hardware Reference Manual 21 For public disclosure ...

Page 22: ...estore power 3 4 Initial Startup A few seconds after powerup the mCOM10 L1500 system UEFI Firmware banner displays on the screen If you do not see any error messages up to this point the board is running properly and ready to be installed and configured for your application 3 4 1 UEFI Firmware Setup Contact GE Intelligent Platforms for technical support Refer to the section Support Service and War...

Page 23: ... USB 3 0 SuperSpeed Two SATA 2 x 3 x controllers SD card reader 3 0 or SDIO controller LPC Bus interface High definition audio General purpose I O SPI bus controller Two SMBus controllers Clock generator The G Series SoC uses the new generation Jaguar embedded processor from AMD that offers the following features Up to four execution cores 40 bit physical addressing 48 bit virtual addressing 32 KB...

Page 24: ... two simultaneous video outputs with multiple modes The G Series SoC integrates the new generation Radeon Sea Islands GPU which supports DirectX 11 1 There is no independent memory dedicated to the GPU video frame buffer so a portion of main memory must be reserved for this purpose Two digital video outputs are provided Analog video is not used Video Outputs Video Output Description Configuration ...

Page 25: ...re supported A combined SATA activity indicator is also provided 4 1 6 USB The mCOM10 L1500 provides eight G Series SoC USB controllers to host serial links through the COM Express connector All ports support USB 2 0 while ports 8 and 9 also support USB 3 0 SuperSpeed The following table provides port mapping between the G Series SoC and the COM Express connector USB Port Assignments Port USB Inte...

Page 26: ...ator starting 4 1 10 Real Time Clock and CMOS RAM The RTC oscillator uses a 32 768 kHz crystal The G Series SoC provides the real time clock RTC and CMOS RAM functions This is powered from the VCC_RTC pin and must be supplied by the carrier prior to ramp up of the standby and main power rails for proper board operation Battery back up if required must also be implemented on the carrier board 4 1 1...

Page 27: ...rectly to the COM Express connector Isolation should be implemented on the carrier board Three status LED outputs from the I210 are decoded in the FPGA to produce four Ethernet link and activity indicators connected to the COM Express connector Note An attached 512 KB serial Flash is provided for the I210 to store Ethernet configuration data such as the MAC address along with optional ROM modules ...

Page 28: ...ous or unintentional changes Once locked it remains locked until reset 4 3 2 I2C Bus The on board I2C bus is also connected to the G Series SoC Sideband Temperature Sensor Interface SB TSI which provides local and remote temperature monitoring of the CPU A standard I2C bus is wired to the COM Express connector The FPGA provides the I2C controller as an LPC bus peripheral The I2C bus is wired to a ...

Page 29: ...tion For battery less systems the carrier board must hold off standby and primary power to meet the five second requirement when the system powers up Once VCC_5V_SBY or VCC_12V is applied the on board standby supplies will power up and the module enters the S5 state To move from standby to active state primary power VCC_12V must be applied and stable with PWR_OK as True and the power button signal...

Page 30: ...ilitates programming of the FPGA For processor debug APU_Sel alone is asserted and the G Series SoC will be the only device in the chain APU_Sel Board_Sel G Series SoC I210 FPGA JTAG Connector JTAG Chain Connections 4 6 Fan Monitor The CPU temperature is monitored and compared with a target temperature A PID controller sets the fan speed output on FAN_PWMOUT accordingly The appropriate fan driver ...

Page 31: ...press plug on the carrier board mCOM10 L1500 Connector Pin Assignments Pin Signal Pin Signal A1 GND B1 GND A2 GBE0_MDI3 B2 GBE0_ACT A3 GBE0_MDI3 B3 LPC_FRAME A4 GBE0_LINK100 B4 LPC_AD0 A5 GBE0_LINK1000 B5 LPC_AD1 A6 GBE0_MDI2 B6 LPC_AD2 A7 GBE0_MDI2 B7 LPC_AD3 A8 GBE0_LINK B8 LPC_DRQ0 A9 GBE0_MDI1 B9 LPC_DRQ1 A10 GBE0_MDI1 B10 LPC_CLK A11 GND B11 GND A12 GBE0_MDI0 B12 PWRBTN A13 GBE0_MDI0 B13 SMB_...

Page 32: ... GND B51 GND A52 RSVD B52 RSVD A53 RSVD B53 RSVD A54 GPI0 B54 GPO1 A55 RSVD B55 RSVD A56 RSVD B56 RSVD A57 GND B57 GPO2 A58 PCIE_TX3 B58 PCIE_RX3 A59 PCIE_TX3 B59 PCIE_RX3 A60 GND B60 GND A61 PCIE_TX2 B61 PCIE_RX2 A62 PCIE_TX2 B62 PCIE_RX2 A63 GPI1 B63 GPO3 A64 PCIE_TX1 B64 PCIE_RX1 A65 PCIE_TX1 B65 PCIE_RX1 A66 GND B66 WAKE0 A67 GPI2 B67 WAKE1 A68 PCIE_TX0 B68 PCIE_RX0 A69 PCIE_TX0 B69 PCIE_RX0 A...

Page 33: ...A92 SPI_MISO B92 DDI0_PAIR5 A93 GPO0 B93 DDI0_PAIR6 A94 SPI_CLK B94 DDI0_PAIR6 A95 SPI_MOSI B95 DDI0_DDC_AUX_SEL A96 TPM_PP B96 USB_HOST_PRSNT A97 TYPE10 B97 SPI_CS A98 SER0_TX B98 DDI0_CTRLCLK_AUX A99 SER0_RX B99 DDI0_CTRLDATA_AUX A100 GND B100 GND A101 SER1_TX B101 FAN_PWMOUT A102 SER1_RX B102 FAN_TACHIN A103 LID B103 SLEEP A104 VCC_12V B104 VCC_12V A105 VCC_12V B105 VCC_12V A106 VCC_12V B106 VC...

Page 34: ... 3 3 V 3 3 V 1000 Mbps 1 Gbps link indicator GBE0_CTREF REF N A Ethernet magnetics center tap reference Floating SATA Signal Pin Type Voltage Supply Description SATA0_TX O SATA AC coupled on module Channel 0 transmit differential pair transmit signals SATA0_RX I SATA AC coupled on module Channel 0 receive differential pair receive signals SATA1_TX O SATA AC coupled on module Channel 1 transmit dif...

Page 35: ...SRX 0 1 I O AC coupled on carrier board Additional receive differential pairs for SuperSpeed USB data USB_HOST_ PRSNT N A N A USB host present on the carrier indicator Not used LVDS eDP Signal Pin Type Voltage Supply Description LVDS_A 0 2 O LVDS LVDS LVDS or eDP differential pairs 0 2 LVDS_A 3 O LVDS LVDS LVDS differential pair 3 Unused for eDP LVDS_A_CK O CMOS 3 3 V 3 3 V LVDS clock or eDP diffe...

Page 36: ...ata from module to carrier SPI_CLK O CMOS 3 3 V 3 3 V Bus clock SPI_POWER O CMOS 3 3 V suspend 3 3 V Power supply for carrier board SPI Connected to 3 3 V standby supply BIOS_DIS 0 1 I CMOS 3 3 V 3 3 V BIOS boot device selection straps DDI Signal Pin Type Voltage Supply Description DDI0_PAIR 0 3 O PCIE AC coupled on module Differential pairs 0 3 DDI0_PAIR 4 6 I CMOS 3 3 V 3 3 V Differential pairs ...

Page 37: ...rm module physical presence Not connected Power and System Management Signal Pin Type Voltage Supply Description PWRBTN I CMOS 3 3 V Suspend 3 3 V Power button SYS_RESET I CMOS 3 3 V Suspend 3 3 V System reset CB_RESET O CMOS 3 3 V Suspend 3 3 V Carrier board reset PWR_OK IO CMOS 3 3 V 3 3 V Main power OK SUS_STAT I CMOS 3 3 V Suspend 3 3 V Suspend status SUS_S3 O CMOS 3 3 V Suspend 3 3 V Suspend ...

Page 38: ...ral purpose input 2 or SDIO data 2 GPI3 O CMOS 3 3 V 3 3 V General purpose input 3 or SDIO data 3 GPO0 O CMOS 3 3 V 3 3 V General purpose output 0 or SDIO clock GPO1 O CMOS 3 3 V 3 3 V General purpose output 1 or SDIO command response GPO2 I CMOS 3 3 V 3 3 V General purpose output 2 or SDIO write protect GPO3 I CMOS 3 3 V 3 3 V General purpose output 3 or SDIO card detection Module Type Definition...

Page 39: ...rd are routed to a connector for use with an external cable Carrier board USB overcurrent monitors may pull the USB_ 0 2 4 6 _ 1 3 5 7 _OC l lines to GND with open drain drivers to indicate that the monitorʹs current limit has been exceeded Do not pull up these lines to 3 3 Von the carrier board this is done on the module PCI Express At the module the PCI Express transmit signals have ac coupling ...

Page 40: ... DBRDY 9 GND 10 TDI 11 DBG_RESET 12 TMS 13 GND 14 1 8V_STBY 15 GND 16 1 8V_STBY 17 DBG_PWRBTN 18 TDO 19 GND 20 TRST 21 APU_RST 22 TCK 23 GND TCK TMS TDI TDO and TRST are the standard IEEE 1149 1 JTAG signals BOARD_SEL and APU_SEL are used to control insertion and removal of certain devices within the JTAG chain Refer to the section Memory DBRDY DBREQ APU_RST DBG_PWRBTN and DBG_RESET are processor ...

Page 41: ...L1500 is 0x0C15 The Subsystem Vendor ID is 0x1775 PCIe Port Assignments Lane Device Connector Width Speed GPP0 mCOMe PCIE0 1 Gen1 2 GPP1 mCOMe PCIE1 1 Gen1 2 GPP2 mCOMe PCIE2 1 Gen1 2 GPP3 mCOMe PCIE3 1 Gen1 2 GFX0 Ethernet Controller 1 Gen1 GFX1 Unused N A N A GFX2 Unused N A N A GFX3 Unused N A N A Configuration GFK 2896 Hardware Reference Manual 41 For public disclosure ...

Page 42: ...oard SMBus Devices Bus Device Function Address 0 CAT34TS02 SPD EEPROM 1010_000x Temperature Sensor 0011_000x 1 I210 Ethernet Controller Unused 5 2 3 I2C Slave Devices The FPGA hosts an I2C bus controller I2C Devices Device Function 7 bit Address AT24C32 Embedded EEPROM 1010_000x AT24C32 User Data EEPROM 1010_001x SB TSI Temperature Sensor 1001_100x 5 2 4 External Interrupts All external interrupts...

Page 43: ...VENT13_L USB_OC_2_3 In GEVENT14_L USB_OC_4_5 In GEVENT15_L USB_OC_6_7 In GEVENT16_L Unused GEVENT17_L SLEEP In GEVENT18_L BLINK Out GEVENT19_L SYS_RESET In GEVENT20_L Unused GEVENT21_L Unused GEVENT22_L SMB_ALERT In GEVENT23_L Unused GPIO32 THRM In GPIO33 PROCHOT Bi GPIO43 SMB0_CLK Bi GPIO45 Unused GPIO47 SMB0_DAT Bi GPIO48 SERIRQ Bi GPIO49 Unused GPIO50 EXCD0_CPPE In GPIO51 EXCD0_PERST Out GPIO52...

Page 44: ...PIO78 SD_DATA1 Bi GPIO79 SD_DATA2 Bi GPIO80 SD_DATA3 Bi GPIO161 SPI_WP Out GPIO162 SPI_CLK Out GPIO163 SPI_MOSI Out GPIO164 SPI_MISO In GPIO165 SPI_CS1 Out GPIO166 SPI_CS2 Out GPIO167 HDA_SDIN0 Bi GPIO168 HDA_SDIN1 Bi GPIO169 HDA_SDIN2 Bi GPIO170 HDA_SDIN3 In Unused GPIO174 In Unused External pull down GPIO184 BATLOW In GPIO227 SMB1_CLK Bi GPIO228 SMB1_DAT Bi 44 GFK 2896 Mini COM Express Type 10 M...

Page 45: ...rt address The lock and unlock codes do not match any internal index addresses Configuration Access Port Address Name Description 0x002E Index Configuration register index pointer 0x002F Data Configuration data access 6 1 1 Index Port The Configuration Index register is an 8 bit read write register used as a pointer into the configuration register file It contains the index of the configuration re...

Page 46: ...rmware version major release number 0x23 Revision Firmware revision minor release number 0x24 Build Info High High byte of the FPGA Build Information 0x25 Build Info Low Low byte of the FPGA Build Information 6 2 1 Logical Device Number This register selects the current logical device Logical Device Number Register Index 0x07 Bit Name Access Default Description 7 0 LDN R W 0x00 Logical device numb...

Page 47: ...vision minor release number 6 2 5 Build Information The Build Information is constantly incrementing a 16 bit value that changes each time the FPGA firmware is built using the make command FPGA Build Info Register Index 0x24 0x25 Bit Name Access Default Description 15 0 BUILD_INFO R Firmware Build Information FPGA Registers GFK 2896 Hardware Reference Manual 47 For public disclosure ...

Page 48: ... device to be activated or deactivated UART Control Registers Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 00 ACTIVATE R W 0 Logical device activation 0 Disabled 1 Enabled 6 3 2 UART Base Address The UART Base Address register sets the I O base address for the UART registers The base address must be aligned on an 8 byte boundary and lie within the range 0x0100 0x03F8 UART Base A...

Page 49: ... Access Default Description 7 04 R 0b0000 Reserved 3 0 IRQ R W 0b0000 Interrupt request line assignment 0b0000 None 0b0001 IRQ1 0b0010 IRQ2 0b0011 IRQ3 0b0100 IRQ4 0b0101 IRQ5 0b0110 IRQ6 0b0111 IRQ7 0b1000 IRQ8 0b1001 IRQ9 0b1010 IRQ10 0b1011 IRQ11 0b1100 IRQ12 0b1101 IRQ13 0b1110 IRQ14 0b1111 IRQ15 FPGA Registers GFK 2896 Hardware Reference Manual 49 For public disclosure ...

Page 50: ...ation 6 R W 0 Reserved 5 TEST_FE R W 0 Framing error test mode When set to 1 the transmitted stop bit is truncated to bit time This bit must be cleared to 0 for normal operation 4 TEST_PE R W 0 Parity error test mode When set to 1 the transmitted parity bit is inverted This bit must be cleared to 0 for normal operation 3 2 FIFO_SIZE R W 0b00 Selects the size of the transmit and receive data FIFOs ...

Page 51: ... deactivated Supervision Control Register LDN 0x0A Index 0x30 Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 ACTIVATE R W 0 Logical device activation 0 Disabled 1 Enabled 6 4 2 Supervision Base Address The Supervision Base Address register sets the I O base address for the supervision registers The base address must be aligned on an 8 byte boundary Supervision Base Address Registe...

Page 52: ...vated or deactivated I2C Control Register LDN 0x0C Index 0x30 Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 ACTIVATE R W 0 Logical device activation 0 Disabled 1 Enabled 6 5 2 I2C Base Address The I2C Base Address register sets the I O base addresses for the I2C controller run time registers The base address must be aligned on an 8 byte boundary I2C Base Address Register LDN 0x0C...

Page 53: ...escription 7 04 R 0b0000 Reserved 3 IRQ R W 0b0000 Interrupt request line assignment 0b0000 None 0b0001 IRQ1 0b0010 IRQ2 0b0011 IRQ3 0b0100 IRQ4 0b0101 IRQ5 0b0110 IRQ6 0b0111 IRQ7 0b1000 IRQ8 0b1001 IRQ9 0b1010 IRQ10 0b1011 IRQ11 0b1100 IRQ12 0b1101 IRQ13 0b1110 IRQ14 0b1111 IRQ15 FPGA Registers GFK 2896 Hardware Reference Manual 53 For public disclosure ...

Page 54: ...ical device to be activated or deactivated Watchdog Timer Control Register LDN 0x14 Index 0x30 Bit Name Access Default Description 7 01 R 0b0000000 Reserved 0 ACTIVATE R W 0 Logical device activation 0 Disabled 1 Enabled 6 6 2 Watchdog Timer Base Address The Watchdog Timer Base Address register sets the I O base addresses for the FFC watchdog timer run time registers The base address must be align...

Page 55: ...010 IRQ2 0b0011 IRQ3 0b0100 IRQ4 0b0101 IRQ5 0b0110 IRQ6 0b0111 IRQ7 0b1000 IRQ8 0b1001 IRQ9 0b1010 IRQ10 0b1011 IRQ11 0b1100 IRQ12 0b1101 IRQ13 0b1110 IRQ14 0b1111 IRQ15 6 6 4 Watchdog Timer Options The Watchdog Timer Options register controls the interrupt and reset outputs of the Watchdog Bit Name Access Default Description 7 02 R 0b000000 Reserved 1 0 RST_EN R W 0 Reset enable 0 NMI_EN R W 0 N...

Page 56: ...cant byte of baud rate divisor 0x1 1 Divisor Latch MSB Most significant byte of baud rate divisor 6 7 1 Receive Buffer This register holds the incoming received data after it has been transferred from the incoming shift register In FIFO mode this register contains received data bytes pulled from the top of the memory buffer UART Receive Buffer Register Offset 0x0 DLAB 0 Bit Name Access Default Des...

Page 57: ...scription 7 TX_XFR R W 0 Transmit DMA transfer enable Automatically cleared when the transfer is complete as indicated by the terminal count 6 RX_XFR R W 0 Receive DMA transfer enable Automatically cleared when the transfer is complete as indicated by the terminal count 5 TX_DMA R W 0 Transmit DMA transfer complete interrupt enable 4 RX_DMA R W 0 Receive DMA transfer complete interrupt enable 3 MO...

Page 58: ...mit Data register A modem status interrupt is cleared by reading the Modem Status register Receive and transmit DMA interrupts are cleared by reading the Interrupt Identification Register when they are the source of the interrupt UART Interrupt Identification Register Offset 0x2 Bit Name Access Default Description 7 06 FIFO R 0b00 Set to 0b11 when FIFO mode is enabled 5 0 TX_DMA R 0 Transmit DMA t...

Page 59: ...b11 56 bytes 256 byte FIFO 0b00 1 byte 0b01 32 bytes 0b10 64 bytes 0b11 128 bytes 5 04 TX_TRIG W 0b00 Transmit FIFO trigger level 16 byte FIFO 0bXX 1 byte 64 byte FIFO 0b00 1 byte 0b01 16 bytes 0b10 56 bytes 0b11 64 bytes 256 byte FIFO 0b00 1 byte 0b01 64 bytes 0b10 224 bytes 0b11 256 bytes 3 0 DMA_MODE W 0 DMA mode select 2 0 TX_CLR W 0 Writing a 1 clears the transmit FIFO This bit is self cleari...

Page 60: ...ed 1 Parity is transmitted and checked as a 0 for odd parity and as a 1 for even parity 4 EVEN_PAR R W 0 Even parity select 0 Odd number of 1s in data parity 1 Even number of 1s in data parity 3 PAR_EN R W 0 Parity enable 0 No parity 1 Parity bit is generated and appended to each outgoing character and is checked on each incoming character 2 STOP R W 0 Sets the number of generated stop bits 0 1 st...

Page 61: ...d to the receive shift register DTR is connected to DSR RTS is connected to CTS OUT1 is connected to RI and OUT2 is connected to DCD 3 0 OUT2 R W 0 Output 2 In Loop back mode connected to Data Carrier Detect input 2 0 OUT1 R W 0 Output 1 In Loop back mode connected to Ring Indicator input 1 0 RTS R W 0 External Request To Send signal control 0 RTS is set to 1 1 RTS is set to 0 0 0 DTR R W 0 Extern...

Page 62: ...it data parity stop bit time In FIFO mode this applies to the character at the top of the FIFO Generates a Receiver Line Status interrupt Cleared when read 3 FE R 0 Framing error Set to 1 when the received character does not have a valid stop bit In FIFO mode this applies to the character at the top of the FIFO Generates a Receiver Line Status interrupt Cleared when read 2 PE R 0 Parity error Set ...

Page 63: ...f external DSR input Equals DTR in loopback mode 4 CTS R 0 Complement of external CTS input Equals RTS in loopback mode 3 DDCD R 0 Delta data carrier detect Indicates that the DCD line has changed state 2 TERI R 0 Trailing edge of ring indicator Indicates that the RI line has changed state from low to high 1 DDSR R 0 Delta data set ready Indicates that the DSR line has changed state 0 DCTS R 0 Del...

Page 64: ...the 33 33 MHz reference clock down to the serial data rate The divisor is a 16 bit value contained in two byte wide registers one for the MSB and one for the LSB For asynchronous mode the clock is set to 16 the bit rate UART Divisor LSB Register Offset 0x0 DLAB 1 Bit Name Access Default Description 7 0 DIV 7 0 R W 0x00 LSB of baud rate generator divisor UART Divisor MSB Register Offset 0x1 DLAB 1 ...

Page 65: ...affected Typically this register should be read early in the boot process Note This register cannot detect software controlled hard or soft resets issued by the SoC Reset Cause Register Offset 0x0 Bit Name Access Default Description 7 VREG_RST R C 0 When set indicates that a CPU power supply regulator under voltage reset occurred Cleared by writing a 1 to the bit 6 WDOG_RST R C 0 When set indicate...

Page 66: ...atchdog timeout caused the last board reset Cleared by writing a 1 to the bit 5 R 0 Reserved 4 DB_RST R C 0 When set indicates that a debug port reset caused the last board reset Cleared by writing a 1 to the bit 3 R 0 Reserved 2 PB_RST R C 0 When set indicates that a push button reset caused the last board reset Cleared by writing a 1 to the bit 1 OVERTEMP R C 0 When set indicates that a processo...

Page 67: ...ata read 0x6 Command read back Command register read 0x7 Reserved Reserved 6 9 1 Clock Prescale The I2C clock frequency is set by a 16 bit prescale value The actual frequency is equal to the FPGA core clock 33 33 MHz divided by five times the prescale value plus one For example a prescale value of 0x42 yields an I2C clock frequency of 99 5 kHz and a prescale value of 0x10 yields an I2C clock frequ...

Page 68: ...Transmit The I2C Transmit register is used to write the data and address control bytes to be sent on the I2C bus It can be written at address offset 0x3 and read back at offset 0x5 I2C Transmit Register Offset 0x3 0x5 Bit Name Access Default Description 7 0 TX R W 0x00 Data or address control byte to be transmitted on the I2C bus 6 9 4 Receive The I2C Receive register is used to retrieve the data ...

Page 69: ...rt bit 6 STO R W 0 Stop Automatically cleared Always read as zero 0 No action 1 Generate a Stop bit 5 RD R W 0 Read Automatically cleared Always read as zero 0 No action 1 Read from slave 4 WR R W 0 Write Automatically cleared Always read as zero 0 No action 1 Write to slave 3 ACK R W 0 Acknowledgement 0 Send ACK when receiver 1 Send NACK when receiver 2 01 R 0b00 Reserved 0 IACK R W 0 Interrupt a...

Page 70: ...ived acknowledge flag from the slave 0 ACK 1 NACK 6 BUSY R 0 SMBus busy 0 Stop detected 1 Start detected 5 AL R 0 Arbitration lost 0 Normal operation 1 Arbitration lost 4 02 R 0b000 Reserved 1 TIP R 0 Transfer in progress 0 Transfer complete 1 Data transfer is in progress 0 IF R 0 Interrupt flag 0 No interrupt is pending 1 Interrupt is pending 70 GFK 2896 Mini COM Express Type 10 Module mCOM10 L15...

Page 71: ...ed 0x8 Control Timer control register 0x9 Reserved 0xA Reload Timer reload register 0xB Reserved 0xC Status Timer status register 0xD Reserved 0xE Interrupt Enable Interrupt Enable Register 0xF Reserved The interrupt and reset count register contents can be changed while the Watchdog timer is unlocked but the new values will not take effect until the Watchdog is serviced The actual timeout interva...

Page 72: ... The reset indication is a sticky bit that is not cleared on a system reset although it is cleared on powerup Watchdog Timer Status Register Offset 0xC Bit Name Access Default Description 7 02 R 0b000000 Reserved 1 0 EXP_RST R C 0 Reset timer expired When 1 indicates that the Watchdog reset timer has expired Cleared by writing a 1 to the bit Sticky bit that retains its value through a system reset...

Page 73: ...ion Level A F Conduction Level D Vibration Random 0 1g2 Hz from 15 to 2000 Hz Shock 40g pk saw tooth 11 ms duration Humidity 10 to 90 RH non condensing Altitude Up to 4 572 m 15 000 ft above sea level Conformal Coating Coating thickness 0 0508 to 0 0762 mm 0 002 to 0 003 in Electrical Power Supply Voltage VRTC 3 V nominal 2 0 to 3 3 V5VSBY 5 V nominal 4 75 to 5 25 V12V 12 V nominal 4 75 to 20 wide...

Page 74: ...Notes 74 GFK 2896 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure ...

Page 75: ...1 is represented by a low electrical signal JTAG Typically used to refer to JTAG boundary scan LPC Bus A low speed interface used for peripheral circuits such as Super I O controllers which typically combine legacy device support into a single IC LVDS Widely used as a physical interface for TFT flat panels LVDS can be used for many high speed signaling applications In this document it refers only ...

Page 76: ...rial EEPROM associated with a bank of memory that contains the characteristics and operating parameters of the memory SPI A four wire clock data in data out and chip select bus typically used for low speed non volatile memories Standard for a synchronous serial data bus with Master Slave devices TAP JTAG boundary scan control port UDIMM Memory module where the address and control bus is directly c...

Page 77: ...gisters 46 I2C Address 52 I2C Control 52 I2C Controller Configuration Registers 52 I2C Controller Run Time Registers 67 I2C IRQ 53 Index Port 45 Interrupt Enable 57 Interrupt Identification 58 Last Reset 66 Line Control 60 Line Status 62 Logical Device Number 46 Modem Control 61 Modem Status 63 Receive 68 Receive Buffer 56 Reset Cause 65 Revision 47 Scratchpad 64 Status 70 Supervision Base Address...

Page 78: ...odem Control 61 Modem Status 63 N Non Volatile Memory 28 P Package Contents 16 PCI Express PCIe 24 PCIe Ports 41 Pin Assignments JTAG 40 Module 31 PCIe Ports 41 Power Distribution 29 Power Reset Sequence 29 Power Supplies 29 Primary VCC_12V 29 R Real Time Clock 26 Receive 68 Receive Buffer 56 Required Materials DDI 19 Reset Cause 65 Revision 47 RTC VCC_RTC 29 S Scratchpad 64 Secure Digital 25 Seri...

Page 79: ...ansmit 68 Transmit Buffer 56 U UART Base Address 48 UART Configuration Registers 48 UART Control 48 UART IRQ 49 UART Mode 50 UART Run Time Registers 56 UEFI Firmware Setup 22 Unpacking and Inspecting Damage 16 Unpacking and Inspection 15 USB Port assignments 25 V Version 46 Video Monitor 19 Video outputs 24 W Watchdog Timer WDT FPGA 28 Watchdog Timer Base Address 54 Watchdog Timer Configuration Re...

Page 80: ...Notes 80 Mini COM Express Type 10 Module mCOM10 L1500 For public disclosure ...

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Page 82: ...GE Intelligent Platforms 1 800 433 2682 1 434 978 5100 www ge ip com GFK 2896 For public disclosure ...

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