GE MAC 5000, Service Manual

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Revision B MAC
™
5000 resting ECG analysis system 2-29
2024917-010
Equipment Overview: Theory of Operation
open drain output of the comparator is used to remove the gate drive
from Q103 which will in turn switch off the com port power. The function
of the integrator is two fold. First it allows high surge currents to exist
for a short time. Secondly the integrator has a much longer recovery time
due to diode CR103 which effectively changes the integration resistor
from 100K
Ω
to 1Meg
Ω
. This long recovery time results in a low duty
cycle when the load is a short circuit. The low duty cycle prevents FET
Q2 from overheating when driving a short circuit.
Since the MAC 3500 contains an internal KISS pump, separate power
control is necessary for this CPU board design to support that product.
An identical Switch / Current Limiter circuit as described above for the
COMM Port Power was added exclusively for the KISS pump.
Thermal Printhead Power / Pixel Test Hardware
The FPGA provides all the interface logic for the thermal print head. A
MOSFET switch controls power. A charge pump voltage doubler driven
by the FPGA provides that switch’s gate drive.
Additional circuitry (currently unsupported) is supplied to allow the
measurement of individual dot resistance for automatic strobe width
compensation and blown dot detection. A switchable constant current
source (6mA) applies a test current to the TPH power bus. Larry then
measures the TPH power bus voltage (one of the four analog inputs he
continuously monitors). By loading a single black dot into the print head
it is possible to measure its resistance. A typical TPH has an average dot
resistance of 650
Ω
. Presuming negligible driver leakage current, a single
enabled dot would drop 3.9V. While there are mitigating influences (off-
pixel driver leakage current and on-pixel driver saturation voltage) that
might make accurate pixel resistance measurements difficult, it is
certainly possible to differentiate pixels of nominal resistance from those
that are blown open.
Super I/O Peripheral Controller
A PC standard Super I/O peripheral controller provides floppy drive
support, two serial channels (one IrDA compatible), and a clock/calendar.
Floppy Drive Support
The Super I/O provides support for a 3.5-inch 1.44MByte IBM format
floppy diskette drive. The FPGA provides DMA like interrupt support for
the floppy controller. A special chip select supplies the DMA
acknowledge signal that gates data to/from the Super I/O floppy
controller via the XBus. To ensure no data is lost, the floppy DMA
request is routed to the ATMEL CPU’s FIQ input.