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FUSHENGTEK Technology WG-7302-E38/J19, User Manual

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FUSHENGTEK Technology WG-7302-E38/J19 User Manual Download Page 25

 

 

WG-7302

 

Page

 

25

 

Document Details

 

 

 

 

 

 

 

WG-7302 User’s Guide

 

7.7 Serial COM1 – COM6 Ports     

4X RS232 and 2X232/422/485 serial ports are available on the WG-7302. 

Description

 

Type 

Signal 

PIN 

Signal 

 

Type 

 

Description

 

Serial 

number 

RS232 signal   

I 

RS_232_A_RX 

1 

2 

RS_232_A_TX 

O 

RS232 signal   

COM1   

RS232 signal 

I 

RS_232_B_RX

 

3 

4 

RS_232_B_TX

 

O 

RS232 signal 

COM2

 

RS232 signal 

I 

RS_232_C_RX

 

5 

6 

RS_232_C_TX

 

O 

RS232 signal 

COM3

 

RS232 signal 

I 

RS_232_D_RX

 

7 

8 

RS_232_D_TX

 

O 

RS232 signal 

COM4

 

RS232 signal 

I 

RS_232_E_RX

 

9 

10 

RS_232_E_TX

 

O   

RS232 signal 

COM5

 

RS232 signal 

I 

RS_232_F_RX

 

11  12 

RS_232_F_TX

 

O   

RS232 signal 

COM6

 

RS485/RS42

2 signal 

I 

RS485_E_D- 

/RS422_E_TxD- 

13  14 

RS_ 

/RS42

 

O   

RS485/RS422 

signal 

COM5

 

RS422 signal 

I 

RS422_E_RxD-

 

15  16 

RS42

 

O   

RS422 signal 

COM5

 

RS485/RS42

2 signal 

I 

RS485_F_D- 

/RS422_F_TxD-

 

17  18 

RS_ 

/RS42

 

O   

RS485/RS422 

signal 

COM6

 

RS422 signal 

I 

RS422_F_RxD-

 

19  20 

RS42

 

O   

RS422 signal 

COM6

 

Ground 

 

Ground 

21  22 

GND 

 

Ground 

Ground 

 

The typical definition of the signals in the COM ports is as follows:

 

Signal   

Description   

TxD 

Transmitted Data sends data to the communications link. The signal is set to the marking state (0V) on 

hardware reset when the transmitter is empty or when loop mode operation is initiated.   

RxD 

Received Data, receives data from the communications link.   

Note1: 

COM_SEL : mode select,Connect jumper to select COM5

、

COM6 mode. 

PIN 

Signal 

Serial number 

1 

2 

RS232 mode 

COM5 

3 

4 

RS485 mode 

5 

6 

RS422 mode 

7 

8 

RS232 mode 

COM6 

9 

10 

RS485 mode 

11 

12 

RS422 mode 

Available cable kit: 

 

COM 

cable

 

Summary of Contents for WG-7302-E38/J19

Page 1: ...WG 7302User sGuide WG 7302 User s Guide WG 7302 ...

Page 2: ... mounted cooler 12 4 Connector Locations 13 4 1 WG 7302 front side 13 4 2 WG 7302 back side 14 5 Connector Definitions 15 6 IO Area Connectors 16 6 1 HDMI Connectors HDMI1 HDMI2 16 6 2 Ethernet Connector 16 6 3 USB Connectors IO Area 18 6 4 DC Power Jack Connector Vin Ext 19 7 Internal Connectors 20 7 1 Power Connector J1 20 7 2 Internal SATA Power Connector SATA_PWR 20 7 3 SATA Serial ATA Disk in...

Page 3: ...9 8 1 mPCIe or mSATA slot 29 8 2 mPCIe slot 30 9 BIOS 31 9 1 Main 31 9 2 Advanced 32 9 2 1 ACPI Settings 33 9 2 2 CPU Configuration 34 9 2 3 OS Selection 35 9 2 4 IDE Configuration 36 9 2 5 CSM Configuration 37 9 2 6 USB Configuration 38 9 2 7 SIO Configuration 39 9 3 Chipset 45 9 3 1 North Bridge 46 9 3 2 South Bridge 50 9 4 Security 53 9 5 Boot 54 9 6 Save Exit 55 Appendix A Customized 56 1 Disp...

Page 4: ...WG 7302 Page 4 Table of Contents WG 7302 User s Guide Appendix D Dimensional drawing 60 ...

Page 5: ... to any product including circuits and or software described or contained in this manual in order to improve design and or performance Specifications listed in this manual are subject to change without notice FUSHENGTEK Technology assumes no responsibility or liability for the use of the described product s conveys no license or title under any patent copyright or mask work rights to these product...

Page 6: ...tion repair or replace the product with a similar product Replacement Product or parts may include remanufactured or refurbished parts or components The warranty does not cover 1 Damage deterioration or malfunction resulting from A Accident misuse neglect fire water lightning or other acts of nature unauthorized product modification or failure to follow instructions supplied with the product B Rep...

Page 7: ... Field Application Engineer FAE Before Contacting Support Please be prepared to provide as much information as possible CPU Board 1 Type 2 Part Number find PN on label 3 Serial Number if available find SN on label Configuration 1 DRAM Type and Size 2 BIOS Revision find the version info in the BIOS Setup 3 BIOS Settings different than Default Settings refer to the BIOS Setup section System 1 O S Ma...

Page 8: ...y 1x LVDS 1x HDMI or 1x LVDS 1x VGA Temperature 40 C to 85 C WG 7302W A11 X Display 1x eDP 1x HDMI or 1x eDP 1x VGA Temperature 40 C to 85 C WG 7302W A12 X Display 2x HDMI or 1x VGA 1x HDMI Temperature 40 C to 85 C Note X CPU model CPU E3805 E3815 E3825 E3826 E3827 E3845 J1900 Use of this Users Guide implies a basic knowledge of PC AT hard and software This manual is focused on describing the E38 ...

Page 9: ...evant connector description 6 Power Button If the board does not start by itself when switching on the ATX PSU AC mains then follow these instructions to start the board Install the Always on Jumper in the Always On position or toggle the PWRBTN_IN signal available in the FRONTPNL connector by momentary shorting pins 3 PWRBTN_IN and pin 2 GND A normally open switch is recommended 7 BIOS Setup Ente...

Page 10: ...TTENTION Risqued explosion avec l é changeinadé quat de la batterie Remplacementseulement par le mê meou un type é quivalentrecommandépar le producteur L é vacuation des batteries usagé esconformé ment àdes indications du fabricant PRECAUCION Peligro de explosió nsi la baterí a se sustituyeincorrectamente Sustituyasolamentepor el mismo o tipoequivalenterecomendadopor el fabricante Dispongalasbater...

Page 11: ...z10W Memory SO DIMM Memory supporting DDR3L1066 1333 MHz up to 8 GB Graphics 2x independent graphic outputs eDP LVDS HDMI1 4a VGA LVDS up to 1920x1200 eDP up to 2560x1600 HDMI up to 1920x1200 VGA up to 2560x1600 Ethernet 2x RJ45 10 100 1000Mb s Ethernet SATA 1x mSATA 1x SATA 2 0 USB 5x USB 2 0 and 1x USB2 0 3 0 4 on front I O 2 internal Serial Ports 4x RS232 3 wire 2x RS232 422 485 I O Features 1x...

Page 12: ... key component on the board is the Intel Atom E38xx SoC Bay Trail 3 3 Integrated pre mounted cooler RJ45 2x HDMI VGA 4xRS232 3 wire Line out Line in Mic in HDA codec Alc662 SO DIMM Memory 1066 1333MHz SIO NCT6106D Realtek RTL8111E Baytrail On board DC DC DCIN eDP mSATA mPCIe RJ45 5x USB2 0 1x USB2 0 1x USB3 0 CH7511B LVDS 18 24 mPCIe 8x GPIOs 2XRS232 422 485 ...

Page 13: ...WG 7302 Page 13 Document Details WG 7302 User s Guide 4 Connector Locations 4 1 WG 7302 front side SPI flash E38XX J19XX SIO ...

Page 14: ...D HDMI 2 LAN1 LAN2 SATA LED USB4 USB3 USB2 USB2 0 USB1 USB3 0 USB2 0 USB3 0 2 0 LCD Power Button SIM VGA SATA1 Vin Ext mPCIe 3G or Wi Fi Always On Pin 1 2 ON Pin 2 3 NC SATA Power GPIO Pin 2 3 Power On Pin 1 2 Reset LVDS or eDP Clear COMS SODIMM mSATA or mPCIe COM 1 6 USB 5 6 Audio BAT COM_SEL ...

Page 15: ...gnals on two paired wires DSI Differential Signaling Input with complementary signals on two paired wires DSIO Differential Signaling Input Output combined DSO and DSI O Output TTL compatible OC Output open collector or open drain TTL compatible OT Output with tri state capability TTL compatible LVDS Low Voltage Differential Signal PWR Power supply or ground reference pins NC Pin not connected Add...

Page 16: ...2 TMD CLK TMDS clock negative DSO 3 3 13 N C Not connected NC 14 N C Not connected NC 15 DDC_CLK DDC clock IO 5 0 16 DDC_DATA DDC data IO 5 0 17 GND Ground PWR 18 VCC5 1 Power 5V PWR 19 TMDS_HPD Hot plug detect I 5 0 Note 1 To protect the external power lines of peripheral devices make sure that the wires have the right diameter to withstand the maximum available current to enclosure of the periph...

Page 17: ... BI_DB pair and is the receive pair in 10Base T and 100Base TX In MDI crossover mode this pair acts as the BI_DA pair and is the transmit pair in 10Base T and 100Base TX MDI 2 MDI 2 In MDI mode this is the third pair in 1000Base T i e the BI_DC pair In MDI crossover mode this pair acts as the BI_DD pair MDI 3 MDI 3 In MDI mode this is the fourth pair in 1000Base T i e the BI_DD pair In MDI crossov...

Page 18: ...3 USB4 in the IO area USB 2 0 ports allowing data transfers up to 480Mb s The USB 3 0 port allowing data transfers up to 5Gb s Two internal USB ports are available via internal 8 pin connectors For USB2 0 cabling it is required to use only High Speed USB cable specified in USB2 0 standard For USB3 0 cabling it is required to use only High Speed USB cable specified in USB3 0 standard ...

Page 19: ...ial differential receive transmit data lines 5V SB5V 5V supply for external devices SB5V is supplied during power down to allow wakeup on USB device activity Protected by 1 0A current limiting circuit for each USB port 6 4 DC Power Jack Connector Vin Ext The DC Power Jack Connector Vin Ext connector must be used to supply the board with 9V 24V Maximum allowed current is 5A Warning Hot Plugging pow...

Page 20: ...2 0 24 0 V 4 Power 9 0 12 0 24 0 V Maximum allowed current on each pin is 5A Available cable kit Power Cable 7 2 Internal SATA Power Connector SATA_PWR Header Pin Signal Description Type 1 1 GND Power Ground PWR 2 5V 5V power input PWR 3 5V 5V power input PWR 4 GND Power Ground PWR Maximum allowed current on each pin is 2A Available cable kit SATA Power Cable ...

Page 21: ...upport SATA 2 0 standard Sata connector pinning PIN Signal Type Ioh Iol Note 1 GND PWR 2 SATA TX 3 SATA TX 4 GND PWR 5 SATA RX 6 SATA RX 7 GND PWR Signal Description SATA RX RX Host transmitter differential signal pair SATA TX TX Host receiver differential signal pair Available cable kit SATA Signal Cable ...

Page 22: ...LVDS LVDS LVDS A1 29 30 Lane 2 n LVDS LVDS LVDS A0 31 32 Lane 1 p LVDS used by eDP LVDS LVDS A0 33 34 Lane 1 n LVDS used by eDP LVDS LVDS ACLK 35 36 Lane 0 p LVDS used by eDP LVDS LVDS ACLK 37 38 Lane 0 n LVDS used by eDP PWR GND 39 40 Hot Plug I Internally pull down 100K ohm Note The LVDS connector supports single and dual channel 18 24bit SPWG panels up to a resolution of 1920x1080 and with limi...

Page 23: ...t LVDS Cable Notes The pin1 voltage of this LVDS interface can be adjusted by PWR_LVDS PWR_LVDS Description pin1 2 pin2 3 X Pin1 of LVDS connector J8 is DC IN X Pin1 of LVDS connector J8 is 5V Warning Short connected to the 1 2 pin the 1 pin voltage of the LVDS connector is equal to the main board input voltage 7 5 Analog Connector VGA The analog monitor interface is available through the VGA conn...

Page 24: ...ormation on USB0 USB1 Header Pin Signal Description Type 1 1 USB5 IO 2 USB5 IO 3 GND Ground PWR 4 USB6 IO 5 USB6 IO 6 GND Ground PWR 7 5V SB5V 5V power PWR 8 5V SB5V 5V power PWR Note1 Signal Description USBx USBx Differential pair works as Data Address Command Bus 5V SB5V 5V supply for external devices SB5V is supplied during power down to allow wakeup on USB device activity Protected by 1 0A cur...

Page 25: ...2_E_TxD O RS485 RS422 signal COM5 RS422 signal I RS422_E_RxD 15 16 RS422_E_RxD O RS422 signal COM5 RS485 RS42 2 signal I RS485_F_D RS422_F_TxD 17 18 RS_485_F_D RS422_F_TxD O RS485 RS422 signal COM6 RS422 signal I RS422_F_RxD 19 20 RS422_F_RxD O RS422 signal COM6 Ground Ground 21 22 GND Ground Ground The typical definition of the signals in the COM ports is as follows Signal Description TxD Transmi...

Page 26: ... Audio with UAA Universal Audio Architecture featuring 24 bit stereo DAC and 20 bit stereo ADCs Description Type Signal PIN Signal Type Description O Line out right 1 2 Line out left O GND 3 4 GND Microphone I Mic right 5 6 Mic left O Microphone PWR GND 7 I Line in right 9 10 Line in left I Available cable kit Audio cable Audio Jack ...

Page 27: ...puts Output These Signals may be controlled or monitored through the use of the KT API V2 Application Programming Interface 7 10 LCD Power LCD_PWR Turn off the LCD screen by momentary shorting pin1 and pin 2 LCD_PWR Description pin1 2 Default position X shut down LVDS Panel 7 11 Clear CMOS JCM1 Connect jumper to clear CMOS settings Don t leave the jumper installed CMOS Description pin1 2 Default p...

Page 28: ...lement hardware controlled always ON by jumper When Always On is selected the board will power up automatically when power is connected The board can still be shut down by PWRBTN_IN power button in activation via PWR AUTO_BTN Description pin1 2 pin2 3 X Default position X Always On selection Pin 1 PWR AUTO_BTN ...

Page 29: ...LEDD O Debug signal PWR GND 15 16 LEDC O Debug signal Debug signal O LEDB 17 18 GND PWR Debug signal O LEDA 19 20 NC NC PWR GND 21 22 RST 1 SATA_RX_P orPCIE_RX2_DN 23 24 3 3V PWR 1 SATA_RX_N or PCIE_RX2_DP 25 26 GND PWR PWR GND 27 28 1 5V PWR PWR GND 29 30 SMB_CLK 1 SATA_TX_N or PCIE_TX2_DN 31 32 SMB_DATA 1 SATA_TX_P or PCIE_TX2_DP 33 34 GND PWR PWR GND 35 36 NC NC PWR GND 37 38 NC NC PWR 3 3V 39 ...

Page 30: ... NC NC CLKN 11 12 NC NC CLKP 13 14 NC NC PWR GND 15 16 NC NC NC NC 17 18 GND PWR NC NC 19 20 NC NC PWR GND 21 22 RST PCIE_RX_DN 23 24 3 3V PWR PCIE_RX_DP 25 26 GND PWR PWR GND 27 28 1 5V PWR PWR GND 29 30 SMB_CLK PCIE_TX_DN 31 32 SMB_DATA PCIE_TX_DP 33 34 GND PWR PWR GND 35 36 USBN PWR GND 37 38 USBP PWR 3 3V 39 40 GND PWR PWR 3 3V 41 42 NC NC PWR GND 43 44 NC NC NC 45 46 NC NC NC 47 48 1 5V PWR N...

Page 31: ...ore the operating system boot begins From the EFI Shell write Exit followed by TAB and Return in order to enter BIOS Menu The BIOS settings will be loaded automatically when loading Restore Default see Save Exit menu In this Users Guide the default settings are indicated by bold Please notice that Restore User Defaults might have different set of default values 9 1 Main Function Option Description...

Page 32: ...I Settings The ACPI Configuration Page CPU Configuration The CPU Configuration Page OS Selection The OS Select Page IDE Configuration The IDE Configuration Page CSM Configuration The CSM Configuration Page USB Configuration The USB Configuration Page SIO Configuration The Super IO configuration Page ...

Page 33: ...ation Enable Hibernation Disabled Enabled Enable or Disable System ability to Hibernate OS S4 Sleep State This option may be not effective with some os ACPI Sleep State Suspend Disabled S3 only suspend to RAM Select the highest APPI sleep state the system will enter when the SUSPEND button is pressed Lock Legacy Resources Disabled Enabled Enable or Disable Lock of Legacy Resources ...

Page 34: ...sable for windows XP Execute Disable Bit Disabled Enabled XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS Hardware Prefetcher Disabled Enabled Enable the mid level Cache L2 streamer Adjacent Cache Line P Disabled Enabled Enable the Mid Level Cache L2 prefetching of adjacent cache lines Intel virtualization Disabled Enabled When enabled a VMM c...

Page 35: ...WG 7302 Page 35 Document Details WG 7302 User s Guide 9 2 3 OS Selection Function Option Description OS Selection Windows 8 X Windows 7 OS Selection ...

Page 36: ...ation Function Option Description Serial ATA SATA Disabled Enabled Enable Disable Serial ATA SATA Mode IDE mode AHCI mode Select IDE AHCI Serial ATA Port 0 Disabled Enabled Enable Disable Serial ATA Port 0 Serial ATA Port 1 Disabled Enabled Enable Disable Serial ATA Port 1 ...

Page 37: ...ption ROM IMMEDIATE execute the trap right away POSTPONED execute the trap during legacy boot Boot option filter UEFI and Legacy Legacy only UEFI only This option controls Legacy UEFI ROMS priority Network Do not launch UEFI only Legacy only Controls the execution of UEFI and Legacy PXE OpROM Storage Do not launch UEFI only Legacy only Controls the execution of UEFI and Legacy Storage OpROM Video ...

Page 38: ... EHCI Hand off Disabled Enabled This is a workaround for OSes without EHCI hand off support The EHCI ownership change should be claimed by EHCI driver USB Massage Storage Driver Disabled Enabled Enable Disable USB Mass Storage Driver Support USB transfer time out 1sec 5sec 10sec 20sec The time out value for Control Bulk and Interrupt transfers Device reset time out 10sec 20sec 30sec 40sec USB mass...

Page 39: ... SIO Configuration Function Option Description Serial Port 1 Enable Disable Serial Port 1 Serial Port 2 Enable Disable Serial Port 2 Serial Port 3 Enable Disable Serial Port 3 Serial Port 4 Enable Disable Serial Port 4 Serial Port 5 Enable Disable Serial Port 5 ...

Page 40: ...able or Disable this Logical Devcie Possible Use Automatic Settings Io 3F8h IRQ4 DMA Io 3F8h IRQ3 4 5 7 9 10 11 12 DMA Io 2F8h IRQ3 4 5 7 9 10 11 12 DMA Io 3E8h IRQ3 4 5 7 9 10 11 12 DMA Io 2E8h IRQ3 4 5 7 9 10 11 12 DMA Allows user to change Device s Resource settings New settings will be reflected on This setup page after system restarts ...

Page 41: ...able or Disable this Logical Devcie Possible Use Automatic Settings Io 3F8h IRQ4 DMA Io 3F8h IRQ3 4 5 7 9 10 11 12 DMA Io 2F8h IRQ3 4 5 7 9 10 11 12 DMA Io 3E8h IRQ3 4 5 7 9 10 11 12 DMA Io 2E8h IRQ3 4 5 7 9 10 11 12 DMA Allows user to change Device s Resource settings New settings will be reflected on This setup page after system restarts ...

Page 42: ...able or Disable this Logical Devcie Possible Use Automatic Settings Io 3F8h IRQ4 DMA Io 3F8h IRQ3 4 5 7 9 10 11 12 DMA Io 2F8h IRQ3 4 5 7 9 10 11 12 DMA Io 3E8h IRQ3 4 5 7 9 10 11 12 DMA Io 2E8h IRQ3 4 5 7 9 10 11 12 DMA Allows user to change Device s Resource settings New settings will be reflected on This setup page after system restarts ...

Page 43: ...able or Disable this Logical Devcie Possible Use Automatic Settings Io 3F8h IRQ4 DMA Io 3F8h IRQ3 4 5 7 9 10 11 12 DMA Io 2F8h IRQ3 4 5 7 9 10 11 12 DMA Io 3E8h IRQ3 4 5 7 9 10 11 12 DMA Io 2E8h IRQ3 4 5 7 9 10 11 12 DMA Allows user to change Device s Resource settings New settings will be reflected on This setup page after system restarts ...

Page 44: ...able or Disable this Logical Devcie Possible Use Automatic Settings Io 3F8h IRQ4 DMA Io 3F8h IRQ3 4 5 7 9 10 11 12 DMA Io 2F8h IRQ3 4 5 7 9 10 11 12 DMA Io 3E8h IRQ3 4 5 7 9 10 11 12 DMA Io 2E8h IRQ3 4 5 7 9 10 11 12 DMA Allows user to change Device s Resource settings New settings will be reflected on This setup page after system restarts ...

Page 45: ...WG 7302 Page 45 Document Details WG 7302 User s Guide 9 3 Chipset Function Option Description North Bridge North Bridge Parameters South Bridge South Bridge Parameters ...

Page 46: ...Details WG 7302 User s Guide 9 3 1 North Bridge Function Option Description Intel IGD Configuration Config Intel IGD Settings Graphics Power Management Control Graphics Power Management Control Options LCD Control LCD Settings ...

Page 47: ...Disabled Enabled Enbale EnableIGD Turbo Enable Disable IGD Turbo disable GFX Boost Disabled Enabled Enable Disable GFX Boost PAVC Disabled LITE Mode SERPENT Mode Enable Disable Protected Audio Video Control DVMT Pre Allocated 64M 96M 128M 160M 192M 224M 256M 288M 320M 352M 384M 416M Select DVMT 5 0 Pre Allocated Fixed Graphics Memory size used by the Internal Graphics Device DVMT Total GfxMem 128M...

Page 48: ... GTT Size 1MB 2MB Select the GTT Size IGD Thermal Disabled Enabled Enable Disable IGD Thermal Spread spectrum clock Disabled Enabled Enable Disable Spread Spectrum clock 9 3 1 2 Graphics Power Management Control Function Option Description RC6 Render Standby Disabled Enabled Check to enable render standby support ...

Page 49: ...ontrol Function Option Description LCD Panel Type VBIOS Default 640 x 480 800 x 600 1024 x 600 1024 x 768 1280 x 800 1280 x 1024 1366 x 768 1400x1050 1440x900 1600x900 1600 x 1200 Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item ...

Page 50: ...WG 7302 Page 50 Document Details WG 7302 User s Guide 9 3 2 South Bridge Function Option Description Azalia HD Audio Azalia HD Audio Options USB Configuration USB Configuration Settings ...

Page 51: ... Detection of the Azalia device Disabled Azalia will be unconditionally disabled Enabled Azalia will be unconditionally Enabled Auto Azalia will be enabled if Azalia HDMI Codec Disabled Enabled Enable Disable internal HDMI codec for Azalia HDMI Port B Disabled Enabled Enable Disable HDMI Port B HDMI Port C Disabled Enabled Enable Disable HDMI Port C ...

Page 52: ...Control Disabled Enabled Control each of the USB ports 0 3 Enable Enable USB per port Disable Use USB Port X Settings USB Port 0 Disabled Enabled Enable Disable USB Port 0 USB Port 1 Disabled Enabled Enable Disable USB Port 1 USB Port 2 Disabled Enabled Enable Disable USB Port 2 Note XHCI mode is disable by default if you need to enable please choose you os in the OS Selection page then ena ble XH...

Page 53: ...WG 7302 Page 53 Document Details WG 7302 User s Guide 9 4 Security Function Option Description Administrator password Set Administrator password User password Set User password ...

Page 54: ...definite waiting BootupNumLock State On Off Select the Keyboard Numlock state Quiet Boot Disabled Enabled Enables or disables Quiet Boot option Fast Boot Disabled Enabled Enables or disables boot with initialization of a minimal set of devices required to launch active boot option Has no effect for BBS boot options Boot Option UEFT Built in EFI Shell Disabled Sets the system boot order ...

Page 55: ... so far to any of the setup options Discard Changes Discard Changes done so far to any of the setup options Restore Defaults Restore Load Default values for all the setup options Save as User Defaults Save the Changes done so far as User Defaults Restore User Defaults Restore the User Defaults to all the setup options UEFI Built in EFI Shell Launch EFI shell from filesystem device Attempts to Laun...

Page 56: ...ions The WG 7302 provides four display interfaces but the chipset supports up to Dualdisplay The following table shows a combination of the display Note Different Display require differentBill of Materials so please let us know your needs before you purchase Default HDMI0 and HDMI1 is available ...

Page 57: ...dress 0x298 Offset 0x01 Attribute R W Size 8 bits Default 0xFF GPIO Data Register BaseAddress 0x298 Offset 0x02 Attribute R W RO Size 8 bits Default N A BIT Description 7 0 0x04 Select GPIO Group 4 GPIO0 GPIO7 Other Reserve BIT Description 7 0 0 The GPIO n Port is programmed as output 1 The GPIO n Port is programmed as input BIT Description 7 0 If GPIO n Port is programmed to be an output then the...

Page 58: ...8H MOV AL 04H OUT DX AL Select GPIO Group4 MOV DX 299H MOV AL 0FFH OUT DX AL Set GPIO 0 7 as Input MOV DX 29AH IN AL DX Read GPIO 0 7 input status MOV DX 299H MOV AL 00H OUT DX AL Set GPIO 0 7 as Output MOV DX 29AH MOV AL 0F0H MOV DX AL Set GPIO 0 3 output low 4 7 output high ...

Page 59: ...se Address 0x298 Offset 0x05 Attribute R W Size 8 bits Default 0x00 Watchdog Timer Counter Register Base Address 0x298 Offset 0x06 Attribute R W Size 8 bits Default N A Sample Code MOV DX 29EH MOV AL 05H OUT DX AL 5 s Reset MOV DX 29EH MOV AL 00H OUT DX AL Disable Watchdog BIT Description 7 4 Reserve 3 Select Watchdog Timer count mode 0 Second Mode 1 Minute Mode 2 0 Reserve BIT Description 7 0 Wat...

Page 60: ...WG 7302 Page 60 Document Details WG 7302 User s Guide Appendix D Dimensional drawing ...

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