Furuno GF-8801, Hardware Specifications, Page: 23 / 31

GF-8801, GF-8802, GF-8803
Hardware Specifications
SE19-410-006-00
19
10.6 UART Wake-up Timing
The start timing specifications of UART input / output are described below.
Figure 10.6-1 shows the UART wake-up timing by the internal reset control (without external reset).
VCC
TXD
RXD
H
L
Valid
t
1ITXD1
t
1IRXD1
Ready
V
RTH_POR
Figure 10.6-1. UART wake-up timing after V
RTH_POR
Table 10.6-1. UART wake-up timing after V
RTH_POR
Item Symbol TYP MAX Unit
Note
Time delay until periodic data
output
t
1ITXD1
3.3 6 sec [*1]
Time delay until the
command input is available
t
1IRXD1
3.3 6 sec [*1]
[*1] after VCC reaches V
RTH_POR
Figure 10.6-2 shows the UART wake-up timing when external reset is used.
RST_N
TXD
RXD
H
L
Valid
t
1XTXD1
t
1XRXD1
Ready
Figure 10.6-2. UART wake-up timing after RST_N
Table 10.6-2. UART wake-up timing after RST_N
Item Symbol TYP MAX Unit Note
Time delay until periodic data
output
t
1XTXD1
3.1 6 sec [*1]
Time delay until the
command input is available
t
1XRXD1
3.1 6 sec [*1]
[*1] after VCC reaches V
RTH_POR