Furuno FS-1503, Service Manual

Page: 22 / 136

2-15
3rd Local Frequency (3Lo)
3Lo is generated by PLL3 (U504). The oscillating frequency varies in accordance with
the class of emission. For example, 456.5 kHz is for J3E (USB) and 456.7 kHz for J2B
(TLX).
2nd Local Frequency (2Lo)
2Lo, 54 MHz, is generated by mixing the output of a reference oscillator (Y501), 36
MHz, with one half of the frequency, 18 MHz.
1st Local Frequency (1Lo)
1Lo is generated by PLL (U502) and DDS (U501). The output frequency is "the set fre-
54.455 MHz + the offset frequency".
The frequency is generated by varying the reference frequency and the frequency divi-
sion ratio of PLL in accordance with the set value of the frequency — the reference fre-
quency of PLL is the output frequency of DDS (Direct Digital Synthesizer). The relation
between the output frequency of DDS and the oscillating frequency of PLL is as follows.
DDS output frequency, fo = (K
×
fc)
÷
2
N
,
where fc is DDS clock frequency (18 MHz)
→
the reference frequency 36 MHz is
divided into 1/2,
N is DDS phase accumulator bit number (32 bits), and
K is DDS phase data input (32 bits)
→
frequency data from CPU.
PLL oscillating frequency, 1Lo = (DDS output frequency, fo
×
N)
÷
M,
Where N is the dividing value of the comparing frequency divider (54 to 84)
→
frequency data from CPU, and
M is the dividing value of the reference frequency divider (fixed to 6).
PLL (VCO) has to oscillate in 54.555 MHz to 84.45499 MHz with the set frequencies of
0.1 MHz to 29.99999 MHz. One VCO with a fixed inductance coil can not cover the
wide frequency range of about 30 MHz. To cover the wide range, the VCO has four coils
with different inductance and selects one corresponding to the set frequency from them.
Further, the two capacitors are switched each other in combination with each coil induc-
tance.