C122-B001-02EN
2-27
2.8 Clock and PCI_Box Control Board (CPCB)
2.8
Clock and PCI_Box Control Board (CPCB)
The CPCB generates system clock signals, it has a function that sends the signals to
SBs, boards in IO_Units, and other boards, and it has an interface connector for
controlling a PCI_Box:
z
Two sets of clock generator circuits are mounted on the CPCB. If one clock
generator circuit fails, MMB firmware control automatically switches operation to
the other one.
However, the whole system must be rebooted for this switching operation.
z
The CPCB contains eight interface connectors (D-SUB 9-pin small connector) for
PCI_Box control.
z
The CPCB contains two UPC interface connectors (D-SUB 9-pin) for un-
interruptable power supply (UPS) control.
z
If only one UPS is connected, connect it to UPC #0.
Figure 2.15 CPCB
UPC interface
PCI-Box interface
CPCB Alarm
Summary of Contents for PRIMEQUEST 440
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