Fujitsu MPG3204AH-E, Product Manual

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C141-E116-01EN 5 - 12
- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of
word unit or byte unit between the host system and the device.
- Bit 2: Always 0.
- Bit 1: Always 0.
- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous
command was being executed. The Error register indicates the additional
information of the cause for the error.
(10) Command register (X'1F7')
The Command register contains a command code being sent to the device. After this register is
written, the command execution starts immediately.
Table 5.3 lists the executable commands and their command codes. This table also lists the
necessary parameters for each command which are written to certain registers before the Command
register is written.