Fujitsu MHV2040AH - Mobile - Hard Drive, Product Manual

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5.5 Ultra DMA Feature Set
C141-E217 5-139
7) The host shall release DD (15:0) within t
AZ
after asserting DMACK-.
8) The device may assert DSTROBE t
ZIORDY
after the host has asserted DMACK-.
Once the device has driven DSTROBE the device shall not release
DSTROBE until after the host has negated DMACK- at the end of an Ultra
DMA burst.
9) The host shall negate STOP and assert HDMARDY- within t
ENV
after
asserting DMACK-. After negating STOP and asserting HDMARDY-, the
host shall not change the state of either signal until after receiving the first
transition of DSTROBE from the device (i.e., after the first data word has
been received).
10) The device shall drive DD (15:0) no sooner than t
ZAD
after the host has
asserted DMACK-, negated STOP, and asserted HDMARDY-.
11) The device shall drive the first word of the data transfer onto DD (15:0). This
step may occur when the device first drives DD (15:0) in step (10).
12) To transfer the first word of data the device shall negate DSTROBE within t
FS
after the host has negated STOP and asserted HDMARDY-. The device shall
negate DSTROBE no sooner than t
DVS
after driving the first word of data onto
DD (15:0).
5.5.3.2 The data in transfer
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.3.3 and 5.6.3.2 for specific timing requirements):
1) The device shall drive a data word onto DD (15:0).
2) The device shall generate a DSTROBE edge to latch the new word no sooner
than t
DVS
after changing the state of DD (15:0). The device shall generate a
DSTROBE edge no more frequently than t
CYC
for the selected Ultra DMA
Mode. The device shall not generate two rising or two falling DSTROBE
edges more frequently than 2t
CYC
for the selected Ultra DMA mode.
3) The device shall not change the state of DD (15:0) until at least t
DVH
after
generating a DSTROBE edge to latch the data.
4) The device shall repeat steps (1), (2) and (3) until the data transfer is complete
or an Ultra DMA burst is paused, whichever occurs first.
5.5.3.3 Pausing an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.3.4 and 5.6.3.2 for specific timing requirements).
a) Device pausing an Ultra DMA data in burst
1) The device shall not pause an Ultra DMA burst until at least one data
word of an Ultra DMA burst has been transferred.