Fujitsu MH2060AH - 60GB UDMA/100 5400RPM 8MB 9.5mm Notebook Hard Disk Drive, Product Manual

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Interface
5-14 C141-E195-02EN
(2) Device Control register (X’3F6’)
The Device Control register contains device interrupt and software reset.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HOB X X X X SRST nIEN 0
- Bit 7: High Order Byte (HOB) is the selector bit that selects higher-order
information or lower-order information of the EXT system command.
If HOB = 1, LBA bits 47 to 24 and the higher-order 8 bits of the sector
count are displayed in the task register.
If HOB = 0, LBA bits 23 to 0 and the lower-order 8 bits of the sector
count are displayed in the task register.
- Bit 2: Software Reset (SRST) is the host software reset bit. When this bit is
set, the device is held reset state. When two device are daisy chained
on the interface, setting this bit resets both device simultaneously.
The slave device is not required to execute the DASP- handshake.
- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the
host. When this bit is 0 and the device is selected, an interruption
(INTRQ signal) can be enabled through a tri-state buffer. When this
bit is 1 or the device is not selected, the INTRQ signal is in the high-
impedance state.
5.3 Host Commands
The host system issues a command to the device by writing necessary parameters
in related registers in the command block and writing a command code in the
Command register.
The device can accept the command when the BSY bit is 0 (the device is not in
the busy status).
The host system can halt the uncompleted command execution only at execution
of hardware or software reset.
When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data
transfer) and the host system writes to the command register, the correct device
operation is not guaranteed.
5.3.1 Command code and parameters
Table 5.3 lists the supported commands, command code and the registers that
needed parameters are written.