PB-91469G-LS-256BGA V12
Chapter 3 Jumpers
UG-910022-13
- 16 -
© Fujitsu Microelectronics Europe GmbH
3.5 DMA Signals: DACK, DEOP, DREQ, DEOTX and IOWRX, IORDX
(JP89 – JP98)
Jumper
Setting
Description
1 – 2
1DACKX0 > V460_DACKX0
2 – 3
V460_DACKX0 > 2DACKX0
4 – 5
4DACKX0 > MCU_D1
JP89
(DACKX0)
DMA
Acknowledge
5 – 6
MCU_D1 > 5DACKX0
1 – 2
1DEOP0 > V460_DEOP0
2 – 3
V460_DEOP0 > 2DEOP0
4 – 5
4DEOP0 > MCU_E1
JP90 (DEOP0)
DMA
termination
output pin
5 – 6
MCU_E1 > 5DEOP0
1 – 2
1DREQ0 > V460_DREQ0
2 – 3
V460_DREQ0 > 2DREQ0
4 – 5
4DREQ0 > MCU_C1
JP91 (DREQ0)
DMA Request
5 – 6
MCU_C1 > 5DREQ0
1 – 2
1DEOTX0 > V460_DEOTX0
2 – 3
V460_DEOTX0 > 2DEOTX0
4 – 5
4DEOTX0 > MCU_D2
JP92
(DEOTX0)
DMA stop
request
5 – 6
MCU_D2 > 5DEOTX0
1 – 2
1DACKX1 > V460_DACKX1
2 – 3
V460_DACKX1 > 2DACKX1
4 – 5
4DACKX1 > MCU_E3
JP93
(DACKX1)
DMA
Acknowledge
5 – 6
MCU_E3 > 5DACKX1
1 – 2
1DEOP1 > V460_DEOP1
2 – 3
V460_DEOP1 > 2DEOP1
4 – 5
4DEOP1 > MCU_F2
JP94 (DEOP1)
DMA
termination
output pin
5 – 6
MCU_F2 > 5DEOP1
1 – 2
1DREQ1 > V460_DREQ1
2 – 3
V460_DREQ1 > 2DREQ1
4 – 5
4DREQ1 > MCU_E2
JP95 (DREQ1)
DMA Request
5 – 6
MCU_E2 > 5DREQ1