Fujitsu MB91F465XA, Application Note

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MB91F465XA EMULATION
Chapter 5 Appendix
MCU-AN-300015-E-V11 - 32 - © Fujitsu Microelectronics Europe GmbH
5.1.3 CIF2 (CUS2) Register
The Customer2 Register (CUS2) is a 32-bit register, at address 0x0008.
The upper 16 bit (B16..31) are called Debug support Register (DBGS).
The lower 16 bit (Bit 0..15) are called DMA support register (DMAS)
Always access the customer 2 register 32-bit wise.
31 0 15
16
DBGS DMAS
Address
0x0008
Debug support Register (DBGS)
The Debug support register is available only in MB88121B. It is reserved in MB88121(A).
Bits 31 - 27 are available in MB88121B, only. For MB88121(A) they are reserved
Address
0x0008
R:
R/W:
Read only
Read/Write
RSV
16
26
R/W
MBSUE
31
R/W
MTE
29
R/W
CYCSE
30
R/W
SDSE
28
R/W
CYCS0E
27
R/W
CYCS0E
bit27
0
1 Output “L“
Cycle Start 0 Enable
Output start of cycle 0
SDSE
bit28
0
1
Start of Dynamic Segment Enable
Output “L“
Output start of dynamic segment
MTE
bit29
0
1
Macrotick start enable
Output “L“
Output start of Macrotick
CYCSE
bit30
0
1
Cycle start enable
Output “L“
Output start of cycle
RSV
bit26 - bit16
Reserved
Write “0”. “0” is read.
MBUSE
bit31
0
1
Message buffer status enable
Output “L“
Output Message buffer status updated