MB91F465XA EMULATION
Chapter 5 Appendix
MCU-AN-300015-E-V11
- 28 -
© Fujitsu Microelectronics Europe GmbH
5.1.2 CIF1 (CCNT) Register / Clock Control Register
The CLOCK CONTROL Register is writeable in DEFAULT_CONFIG (CCSV[5:0] = 00 0000)
or CONFIG state (CCSV[5:0] = 00 1111), only
RSV
31
9
R/W
SDIV[1:0]
8
7
R/W
RSV
6
R/W
Address
0x0004
PON
bit0
0
1
R:
Initial value
0x00000000
STOP
5
R/W
RCLK
4
R/W
PON
0
R/W
SSEL
1
R/W
PMUL[1:0]
3
2
R/W
Stop PLL oscillator
PLL Oscillator Enable
Enable PLL oscillator
SSEL
bit1
0
1
System Clock Selection
PMUL[1:0]
bit3 - bit2
0
1
0
0
0
1
1
1
Select the oscillation clock (X0/X1)
Supply the system clock for FlexRay Controller
Select the PLL clock
PLL Multiplier Selection
X0/X1 (4MHz) x 20 (80MHz)
X0/X1 (5MHz) x 16 (80MHz)
X0/X1 (8MHz) x 10 (80MHz)
X0/X1 (10MHz) x 8 (80MHz)
RCLK
bit4
0
1
RAM Clock Selection (MB88121A/B only)
Select System Clock
Select System Clock divided by 2
STOP
bit5
0
1
Clock Stop
Stop the system clock for FlexRay Controller
These bits are reserved. Always write “0”. “0” is read.
RSV
bit6
Reserved
SDIV[1:0]
bit8 - bit7
0
1
0
0
0
1
1
1
Division for system clock (MB88121A/B only)
System clock is divided by 1
System clock is divided by 2
System clock is divided by 4
System clock is divided by 8
These bits are reserved. Always write “0”. “0” is read.
RSV
bit31 - bit9
Reserved
R/W:
Read only
Read/Write
