Fujitsu MB91401 Datasheet Download Page 40 | Manualshive

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MB91401

40

(Continued)

* : The attribute is different according to the bit.

Address

Register

Block

++++

0

++++

1

++++

2

++++

3

0110_0028

H

SMI_CMD[R/W]

00000000-00000000





SIM IF

0110_002C

H

SMI_CMD_ST

[R/W]

00XXXXXX









0110_0030

H

SMI_DATA [R/W]

00000000-00000000





0110_0034

H

SMI_POLLINTVL [R/W]

00000000-00000000





0110_0038

H

SMI_PHY_ADD

[R/W]

00000XXX









SIM IF

0110_003C

H

SMI_CONTROL

[R/W]

111XXXXX









0110_0040

H

SMI_STATUS[R]

XXXXXXXX









0110_0044

H

SMI_INTENABLE

[R/W]

0XXXXXXX









0110_0048

H

SMI_MDCDIV

[R/W]

01011XXX









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Summary of Contents for MB91401

Page 1: ...he board has the External interface for high speed data communication with various external hosts USB ports as general purpose interfaces and various card interfaces FEATURES Encryption and authentication processing by hardware accelerator function The LSI performs processing five times faster than by the conventional combination of encryption authentication hardware macros and software or about 4...

Page 2: ...r to pass or discard packets when this layer 3 network layer IP addresses or layer 4 transport layer TCP UDP port numbers match conditions Outside interface with telecommunication facility EXTERNAL INTERFACE MB91401 is equipped it with the register for the communication and with mass sending and receiving FIFO that achieves a large amount of data sending and receiving Host functions include proces...

Page 3: ... The CompactFlash interface is a memory and I O mode correspondence It corresponds to the I O of data such as not only the memory card but also the communication cards I2 C Interface Master slave sending and receiving For standard mode 100 Kbps Max ...

Page 4: ... 161 100 60 125 182 231 215 162 101 59 124 181 230 216 163 102 58 123 180 229 228 227 226 225 224 223 222 221 220 219 218 217 164 103 57 122 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 104 56 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 55 2 1 INDEX 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 20 19 A B C D E ...

Page 5: ... 86 SOUT0 146 TCK 206 NMIX 27 RDX 87 INT6 147 PLLS 207 VDDI 28 WRX2 88 A6 148 SCK1 208 VDDE 29 CSX0 89 A5 149 SOUT1 209 VSS 30 N C 90 A8 150 INT7 210 A0 31 D0 91 A11 151 A9 211 VDDI 32 D2 92 A14 152 A12 212 A1 33 D5 93 A17 153 A15 213 VSS 34 D9 94 A19 154 A18 214 VDDE 35 D12 95 A22 155 A20 215 VDDI 36 D15 96 WRX3 156 A23 216 D8 37 VSS 97 WRX1 157 RDY 217 VSS 38 D17 98 CSX1 158 WRX0 218 D26 39 D18 ...

Page 6: ...TCK 1 TRST 1 TMS 1 UCLK48 1 TDI 1 UCLKSEL 1 TDO 1 UDP 1 UDM 1 VPD 1 CFD15 to CFD0 16 TEST3 to TEST0 4 CFA10 to CFA0 11 CFCE2X CFCE1X 2 SIN1 SIN0 2 CFREGX 1 SOUT1 SOUT0 2 CFCD2X CFCD1X 2 SCK1 SCK0 2 CFVS1X 1 CFRDY CFIREQ 1 A23 to A0 24 CFWAITX 1 D31 to D0 32 CFVCC3EX 1 RDX 1 CFRESET 1 WRX3 to WRX0 4 CFOEX 1 CSX0 CSX1 CSX6 3 CFWEX 1 RDY 1 CFIORDX 1 CFIOWRX 1 MCLKO 1 SDA 1 SCL 1 MB91401 BGA 240P M01 ...

Page 7: ...se pins determine the operation mode of the LSI Always set this bit to 001 Pin name Pin no Polarity I O Circuit Function application OSCEA 12 IN G Crystal oscillation input pin Input pin of crystal oscillation cell OSCC 145 Nega tive IN D Crystal oscillation control input pin Oscillation control pin of crystal oscillation cell 0 Oscillation 1 Oscillation stop OSCEB 10 OUT G Crystal oscillation out...

Page 8: ...rve as the emulator data bus when an ICE is connected Pin name Pin no Polarity I O Circuit Function application TCK 146 IN E JTAG test clock pin Note Please input 1 when unused TRST 78 IN E JTAG test reset pin Note Please input 0 when unused TMS 7 IN E TAP controller mode select pin Note Please input 1 when unused TDI 5 IN E JTAG test data input pin JTAG test serial data input pin Note Please inpu...

Page 9: ...output pins Serial data output pin of UART built in FR core SCK1 SCK0 148 14 I O B Serial clock I O pins Serial clock input output pin of UART built in FR core Pin name Pin no Polarity I O Circuit Function application A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 156 95 26 155 94 154 93 24 153 92 23 152 91 22 151 90 21 88 89 20 17 18 212 210 OUT B Address ou...

Page 10: ...CSX0 159 98 29 Nega tive OUT B Chip select output pins 3 bit chip select signal pin Output the L level when accessing to external memory RDX 27 Nega tive OUT B Read strobe output pin Read strobing signal pin Output the L level when read accessing WRX3 WRX2 WRX1 WRX0 96 28 97 158 Nega tive OUT B Write strobing output pins Write strobing signal pin Output the L level when write accessing MCLKO 25 OU...

Page 11: ...112 45 IN D Receive data input pins 4 bit data input from PHY device COL 173 Posi tive IN D Collision detection input pin When TXEN signal is active and 1 the collision is recognized The collision is not recognized without these conditions TXCLK 46 IN D Clock input for transfer pin It becomes synchronous of MII when transmitting The frequency is 2 5 MHz at 10 Mbps and 25 MHz at 100 Mbps TXEN 43 Po...

Page 12: ... 177 118 51 I O B External data GPIO input output pins The I O terminal of data bus bit of bit7 to bit0 with an external host Note When EXIS16 0 input it becomes the I O terminal of GPIO7 to GPIO0 EXRDX 117 Nega tive IN D External read strobing input pin Read strove input pin from external host EXWRX 176 Nega tive IN D External write strobing input pin Write strove input pin from external host EXI...

Page 13: ...h 25 Ω to 30 Ω 27 Ω recommended external series load resistors 1 5 kΩ pull up resistors and about 100 kΩ resistors Input 0 when the USB macro is unused USBINS 182 IN D USB insert input pin USB socket input detection pin Be sure to input 0 when not using USB macro UCLK48 6 IN D 48 MHz input external clock input pin This pin inputs an external 48 MHz clock signal The USB macro operates based on this...

Page 14: ...CFD7 to CFD0 When L level is output odd number byte access of the word is shown CFCE1X 63 Nega tive OUT B CF card enable output pin Byte access output pin to CompactFlash card side Note Supported for access to CFD7 to CFD0 When L level is output at word access even number byte access of the word is shown When the byte is accessed the even number byte and odd number byte access become possible beca...

Page 15: ...rd side 0 It is shown that there is a wait demand at the cycle under execution 1 It is shown that there is no wait demand at the cycle under execution CFVCC3EX 234 Nega tive OUT B CF3 3 V power enable output pin Outputs L level when the CompactFlash card is operable at 3 3 V The output signal enables 3 3 volt power supply to the CompactFlash card The pin outputs L level only when the CFVS1X pin de...

Page 16: ...Pin name Pin no Polarity I O Circuit Function application PLLVDD 199 Power supply V E APLL dedicated power supply pin This pin is for 1 8 V power supply pin PLLVSS 197 GND V S APLL dedicated GND Pin VDDE 83 196 202 208 214 220 226 232 238 Power supply V E 3 3 V power supply pin VDDI 195 200 203 207 211 215 219 223 227 231 235 239 Power supply V E 1 8 V power supply pin VSS 1 19 37 55 193 198 201 2...

Page 17: ...evel input Value of pull down resistance approx 33 kΩ Typ B CMOS level output CMOS level input C USB I O Digital output Digital output Digital input Digital output Digital output Digital input D input D input Differential input Full D output Full D output Low D output Low D output Direction Speed D D ...

Page 18: ...it Remarks D CMOS level input E With pull up CMOS level input Value of pull up resistance approx 33 kΩ Typ F CMOS level output G Oscillation circuit Digital input Digital input Digital output Digital output Oscillation output Control ...

Page 19: ...t the oscillation characteristic of APLL may receive the influence of power supply variation Therefore the power supply is recommended to be separated also on the mounting base Separation of power supply pattern recommended Take measures to reduce impedance for example by using as wide a power pattern as possible The recommendation example is shown as follows For two power supplies for digital and...

Page 20: ...the pins of the same potential are internally connected in the device to avoid abnormal operations including latch up However you must connect the pins to external power supply and a ground line to lower the electro magnetic emission level to prevent abnormal operation strobe signals caused by the rise in the ground level and to conform to the total output current rating The power pins should be c...

Page 21: ...when connecting it with ICE Resistance must be mounted near the terminal ICLK of this LSI when you design the printed wiring board 1 Use the line inter connect to flow the rating current or more 2 The change circuit might become necessary and refer to Precaution when designing 3 Mount resistance near the terminal ICLK of MB91401 Attached cable Part number Remarks FPC cable FH10A 30S 1SH Maker Hiro...

Page 22: ...30 series MB2197 01 Hardware Manual Evaluation MCU terminal name Pin treatment RST To be connected the RST terminal with the reset output circuit in the user system Others To open Signal line name Wiring regulations ICLK ICS2 to ICS0 ICD3 to ICD0 BREAKI The total wiring length of each signal From evaluation MCU pin to the emulator interface connector pin is made within 50 mm The difference of the ...

Page 23: ...t the natural frequency of the crystal oscillator and propagated into the LSI Circuit constant on external substrate Pin name Function OSCC Oscillation control terminal of crystal oscillation cell OSC OSCEA Input terminal of crystal oscillation cell OSC OSCEB Output terminal of crystal oscillation cell OSC Circuit constants Description C1 C2 C3 External load capacity L Inductance Rr Dumping resist...

Page 24: ...ocessed Holding request withdrawal demand function OFF When accessing to the storage destination of encryption authentication processing data the encryption authen tication accelerator should hold an internal bus of this LSI Therefore when the encryption authentication accelerator are used it should be set that the holding request withdrawal doesn t demand Please set the HRCL register that sets th...

Page 25: ...that the program execution of CPU stops Refer to the paragraph of the function explanation of the watchdog timer for the condition of applying to this exception There is a possibility that watchdog reset is not generated when entering the above mentioned state by the reckless driving of the system In that case please specify reset INIT from external INITX terminal Restrictions Clock control block ...

Page 26: ...y at the control register of the instruction cash and RAM mode immediately before the instruction of RETI If one of the instructions listed below is executed the SSP or USP value is not used as the R15 value and as a result an incorrect value is written to memory Only ten following kinds of instructions that specify R15 as Ri correspond As for R15 there are no realities When R15 is accessed from t...

Page 27: ... relevant area When enabling prefetch to the area set to the Little endian give the access to the corresponding area as word 32 bits access limitation In the byte and the half word access it is not possible to access it correctly DMA Do not transfer DMA to instruction RAM Bit Search Module BSD0 BSD1 and the BDSC register are only the word accesses ...

Page 28: ...to added The following interrupt handler Interrupt resource NMI request tool Interrupt number 13 decimal 0D hexadecimal Offset 3C8H TBR is default address 000FFFC8H Additional program STM R0 R1 LDI B00H R0 B00H is address of the break resource register LDI 0 R1 STB R1 R0 Clear the break resource register LDM R0 R1 RETI Trace mode If the trace mode is set to Full trace mode during debug in full tra...

Page 29: ... connected to bus of bus controller FR core E Crystal Unit B T USB IF CompactFlash IF I2 C Bus DH INT NMI MUX External IF GPIO Ext IF PORT DSU IF D RAM 8 KB 10 100 Ethernet MAC Controller L3 L4 Filtering I Cach 4 KB I2 C IF DMAC CLKIN USB CLK 48 MHz CARD IF R HMAC MD5 SHA1 DES 3DES IPsec Accelerator IKE Accelerator Serial IF 2ch MB91401 OSC USB Function Rev2 0FS CLK Cont PLL DSU FLASH UART INT Tim...

Page 30: ...and can be specified directly during an instruction The direct addressing area varies as shown below depending on the size of access data Memory Map The memory space of the macro consists of the following areas byte data access 0 0FFH half word data access 0 1FFH word data access 0 3FFH I O I O 0000 0000H 0000 0400H 0001 0000H 0002 0000H 0003 F800H 0004 0000H FFFF FFFFH I bus RAM 4 KB D bus RAM 8 ...

Page 31: ...f these 16 registers the registers listed below are intended for special applications for which some instructions are enhanced R13 Virtual accumulator R14 frame pointer R15 Stack pointer The initial values of R0 to R14 after a reset are indeterminate R15 is initialized to 00000000H SSP value 0000 0000H AC FP R0 R1 R12 R13 R14 R15 SP XXXX XXXXH XXXX XXXXH 32 bits Initial Value ...

Page 32: ...rates in the operation mode corresponding to the register setting The mode register is set only by an INIT level reset cause The user program cannot access this register However as an exception when the macro shifts to emulation mode by INTE instruction or shifts to emulation mode by a break at a debug using ICE this register is mapped at 0000_07FDH Select this function when using ICE perform the ...

Page 33: ...rts this bus mode this macro cannot use the single chip or internal ROM external bus mode but can use the external ROM external bus mode only Access mode Access mode indicates the mode that controls the external data bus width and is specified by the WTH1 WTH0 bits and the DBW1 DBW0 bits within ACR0 to ACR7 Area Configuration Registers Bus mode The FR family has three bus modes described below Ple...

Page 34: ...XXX W XXXXXXXX TMR0 XXXXXXXX R XXXXXXXX Reload Timer 0 0000_004CH TMCSR0 0000 R W 00000000 0000_0050H TMRLR1 XXXXXXXX W XXXXXXXX TMR1 XXXXXXXX R XXXXXXXX Reload Timer 1 0000_0054H TMCSR1 0000 R W 00000000 0000_0058H TMRLR2 XXXXXXXX W XXXXXXXX TMR2 XXXXXXXX R XXXXXXXX Reload Timer 2 0000_005CH TMCSR2 0000 R W 00000000 Address Register Block 0 1 2 3 0000_0000H 0000_003CH Reserved 0000_0040H EIRR R W...

Page 35: ...000_0204H DMACB0 00000000 00000000 R W 00000000 00000000 0000_0208H DMACA1 00000000 00000000 R W 0000XXXX XXXXXXXX 0000_020CH DMACB1 00000000 00000000 R W 00000000 00000000 0000_0210H DMACA2 00000000 00000000 R W 0000XXXX XXXXXXXX 0000_0214H DMACB2 00000000 00000000 R W 00000000 00000000 0000_0218H DMACA3 00000000 00000000 R W 0000XXXX XXXXXXXX 0000_021CH DMACB3 00000000 00000000 R W 00000000 0000...

Page 36: ...444H ICR04 R W 11111 ICR05 R W 11111 ICR06 R W 11111 ICR07 R W 11111 0000_0448H ICR08 R W 11111 ICR09 R W 11111 ICR10 R W 11111 ICR11 R W 11111 0000_044CH ICR12 R W 11111 ICR13 R W 11111 ICR14 R W 11111 ICR15 R W 11111 0000_0450H ICR16 R W 11111 ICR17 R W 11111 ICR18 R W 11111 ICR19 R W 11111 0000_0454H ICR20 R W 11111 ICR21 R W 11111 ICR22 R W 11111 ICR23 R W 11111 0000_0458H ICR24 R W 11111 ICR2...

Page 37: ...00_0648H ASR2 XXXXXXXX R W XXXXXXXX ACR2 XXXXXXXX R W XXXXXXXX 0000_064CH ASR3 XXXXXXXX R W XXXXXXXX ACR3 XXXXXXXX R W XXXXXXXX 0000_0650H ASR4 XXXXXXXX R W XXXXXXXX ACR4 XXXXXXXX R W XXXXXXXX 0000_0654H ASR5 XXXXXXXX R W XXXXXXXX ACR5 XXXXXXXX R W XXXXXXXX 0000_0658H ASR6 XXXXXXXX R W XXXXXXXX ACR6 XXXXXXXX R W XXXXXXXX 0000_065CH ASR7 XXXXXXXX R W XXXXXXXX ACR7 XXXXXXXX R W XXXXXXXX 0000_0660H A...

Page 38: ...0FFCH Reserved Address Register Block 0 1 2 3 0000_1000H DMASA0 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX DMAC 0000_1004H DMADA0 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000_1008H DMASA1 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000_100CH DMADA1 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000_1010H DMASA2 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000_1014H DMADA2 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0...

Page 39: ... 00000000 DLCR9 R W 00000000 DLCR10 R W 00000000 DLCR11 R W 00000000 0110_000CH DLCR12 R W 00000000 DLCR13 R W 00000000 0110_0008H MAR8 R W 00000000 MAR9 R W 00000000 MAR10 R W 00000000 MAR11 R W 00000000 0110_000CH MAR12 R W 00000000 MAR13 R W 00000000 MAR14 R W 00000000 MAR15 R W 00000000 0110_0008H BMPR10 00000000 BMPR11 00000111 0110_000CH BMPR12 00000000 BMPR14 00000000 0110_0010H BMPR8 00000...

Page 40: ...0000 00000000 SIM IF 0110_002CH SMI_CMD_ST R W 00XXXXXX 0110_0030H SMI_DATA R W 00000000 00000000 0110_0034H SMI_POLLINTVL R W 00000000 00000000 0110_0038H SMI_PHY_ADD R W 00000XXX SIM IF 0110_003CH SMI_CONTROL R W 111XXXXX 0110_0040H SMI_STATUS R XXXXXXXX 0110_0044H SMI_INTENABLE R W 0XXXXXXX 0110_0048H SMI_MDCDIV R W 01011XXX ...

Page 41: ...00 0XXXXXXX 0114_0014H EXIFSR R 00000000 00XXXXXX 0114_0018H EXIFRXSR 00000000 00000000 R 00000000 00000000 0114_001CH EXIFTXSR 00000000 00000000 R 00000000 00000000 0114_0020H PIOCR R W 00000000 GPIO 0114_0024H PIODR R W Connecting destination Address Register Block 0 1 2 3 0500_03E0H IR R W 00000000 DR R W 10000011 Reserved RR R W 00000000 CompactFLASH IF 0501_0000H to 0501_07FFH AMR Attribute M...

Page 42: ...0 CONT3 R W XXXXXXXX_XXX00000 0540_0028H CONT4 R W XXXXXXXX_XXX00000 CONT5 R W XXXXXXXX_XXXX00XX 0540_002CH CONT6 R W XXXXXXXX_XXXX00XX CONT7 R W XXXXXXXX_XXX00000 0540_0030H CONT8 R W XXXXXXXX_XXX00000 CONT9 R W XXXXXXXX_0XXX0000 0540_0034H CONT10 R W XXXX0000_X000000X TTSIZE R W 00010001 00010001 0540_0038H TRSIZE R W 00010001 00010001 0540_003CH to 0540_003FH Reserved 0540_0040H RSIZE0 R XXXXXX...

Page 43: ...5 R W XXXX0XXX XX000000 0540_0070H to 0540_007BH Reserved 0540_007CH RESET R W XXXXXXXX XXXXXX00 0540_0080H to 0540_FFFFH Reserved Address Register Block 0 1 2 3 0580_0000H MACRORR W R 00000000 00000001 CARDSR R W 00000000 00000000 Chip Register 0580_0004H CARDIMR R W 00000000 00000000 CARDISR R 00000000 00000000 0580_0008H USBPLLRP R W 00000000 00000000 ...

Page 44: ...H NMI request 15 0F FH fixed 3C0H 000FFFC0H Ethernet MAC IF 16 10 ICR00 3BCH 000FFFBCH 4 Authentication macro 17 11 ICR01 3B8H 000FFFB8H 5 IPSec Accelerator Code macro 18 12 ICR02 3B4H 000FFFB4H 8 EX IF GPIO 19 13 ICR03 3B0H 000FFFB0H 9 USB I2 C CARD IF 20 14 ICR04 3ACH 000FFFACH External interrupt 5 21 15 ICR05 3A8H 000FFFA8H External interrupt 6 22 16 ICR06 3A4H 000FFFA4H External interrupt 7 23...

Page 45: ...F ICR31 340H 000FFF40H System reserved 48 30 ICR32 33CH 000FFF3CH System reserved 49 31 ICR33 338H 000FFF38H System reserved 50 32 ICR34 334H 000FFF34H System reserved 51 33 ICR35 330H 000FFF30H System reserved 52 34 ICR36 32CH 000FFF2CH System reserved 53 35 ICR37 328H 000FFF28H System reserved 54 36 ICR38 324H 000FFF24H System reserved 55 37 ICR39 320H 000FFF20H System reserved 56 38 ICR40 31CH ...

Page 46: ...t occurs the MHALTI bit in the HRCL register is set to 1 suppressing DMA transfer To permit DMA transfer clear the MHALTI bit to 0 at the end of the NMI routine Interrupt source Interrupt number Interrupt level Offset Address of TBR default RN Decimal Hexa decimal System reserved 68 44 2ECH 000FFEECH System reserved 69 45 2E8H 000FFEE8H System reserved 70 46 2E4H 000FFEE4H System reserved 71 47 2E...

Page 47: ... of the VDDE pins Apply equal potential to all of the VDDI pins Fix all of the VSS pins at 0 V Leave N C pins open Parameter Symbol Rating Unit Remarks Min Max Power supply voltage 1 I O VDDE VSS 0 3 VSS 4 0 V Internal VDDI VSS 0 3 VSS 2 5 V Analog power supply voltage PLLVDD VSS 0 3 VSS 4 0 V 2 Input voltage 1 VI VSS 0 3 VDDE 0 3 V Output voltage 1 VO VSS 0 3 VDDE 0 3 V L level maximum output cur...

Page 48: ...erating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand Parameter Symbol Value Unit Min Typ Max ...

Page 49: ...ge VOH VDDE 3 0 V IOH 4 0 mA VDDE 0 5 V L level output voltage VOL VDDE 3 0 V IOH 4 0 mA 0 4 V Input leak current ILI VDDE 3 6 V VSS VI VDDE 5 µA Pull up resistance RPULU TCK TRST TMS TDI TDO CFCD2X CFCD1X CFVS1X CFRDY CFWAITX 10 33 80 kΩ Pull down resistance RPULD CFRESET 10 33 80 kΩ Power supply current ICC VDDE VDDI 1 8 V VDDE 3 3 V fc 50 MHz T B D mA VDDI T B D mA Input capacitance CIN Without...

Page 50: ...fer in the high impedance state when the VDDE or VSS voltage is applied to the bidirectional pin Parameter Symbol Pin Conditions Value Unit Remarks Min Typ Max H level output voltage VOH IOH 100 µA VDDE 0 2 VDDE V L level output voltage VOL IOL 100 µA 0 0 2 V H level output current IOH VOH VDDE 0 4 V 20 mA L level output current IOL VOL 0 4 V 20 mA output short circuit current IOS 300 mA 1 Input l...

Page 51: ...he above voltage range is referred to as common mode input voltage range 3 Output Levels VOL VOH The output driving performance levels of the driver are 0 3 V or less to 3 6 V 1 5 kΩ load in the low state VOL and 2 8 V or more to ground 1 5 kΩ load in the high state VOH Parameter Symbol Value Unit Remarks Min Max Input Levels High driven VIH 2 0 V 1 Low VIL 0 8 V 1 Diffential Input Sensitivity VDI...

Page 52: ...The cross voltage of the external differential output signals D and D falls within the range from 1 3 V to 2 0 V 5 Terminations VTERM VTERM indicates the pull up voltage at the upstream port D Max 2 0 V Max 1 3 V D VCRS standard range ...

Page 53: ...s Min Max Input clock frequency Fclkcyc XINI External clock 10 0 50 0 MHz Fclkcyc OSCEA OSCEB Oscillation 10 0 50 0 MHz Internal operating clock frequency FR70E peripheral module Fclkin 50 0 MHz Internal operating clock frequency USBC Fusop 48 0 MHz Internal operating clock frequency I2 C IF Fi2op 12 5 MHz External memory clock frequency MCLKO 50 0 MHz AC measurement condition Load condition VIH V...

Page 54: ...heral module Parameter Symbol Pin Conditions Value Unit Remarks Min Max Reset input time trstl INITXI After power supply input clock stabilization At unusing of PLL 5 tcp ns At using of PLL 600 1 µs PLL reset input time tprstl PLLS At using of PLL 1 µs INITXI PLLS trstl tprstl ...

Page 55: ...csh CSX2 to CSX0 MCLKO 0 tcycp 2 7 ns WRX delay time tchwrl WRX3 to WRX0 MCLKO 1 9 ns WRX delay time tchwrh WRX3 to WRX0 MCLKO 1 9 ns Data delay time tchdv D31 to D0 MCLKO 0 tcycp 2 7 ns RDX delay time tchrdl RDX MCLKO 1 9 ns RDX delay time tchrdh RDX MCLKO 1 9 ns Data setup tdsrh D31 to D0 MCLKO 19 ns Data hold trhdx D31 to D0 MCLKO 1 ns tcycp tchav tchcsl tchwrl tchdv tchrdl tdsrh tchrdh tchwrh ...

Page 56: ...MB91401 56 4 Ready input Parameter Symbol Pin Typical timing Value Unit Remarks Min Max RDY setup trdys RDY MCLKO 19 ns RDY hold trdyh RDY MCLKO 1 ns MCLKO RDY trdys trdyh trdys trdyh ...

Page 57: ...k mode 8 timcycp ns SCLK SOUT delay time tslov SOUT1 SOUT0 80 80 ns Valid SIN SCLK tivsh SIN1 SIN0 100 ns SCLK valid SIN hold time tshix SIN1 SIN0 60 ns Serial clock H Pulse Width tshsl SCK1 SCK0 External shift clock mode 4 timcycp ns Serial clock L Pulse Width tslsh SCK1 SCK0 4 timcycp ns SCLK SOUT delay time tslov SOUT1 SOUT0 150 ns Valid SIN SCLK tivsh SIN1 SIN0 60 ns SCLK valid SIN hold time t...

Page 58: ...MB91401 58 Internal shift clock mode External shift clock mode SCK1 SCK0 SOUT1 SOUT0 SIN1 SIN0 tscyc tslov tivsh tshix VOL VOL VOH SCK1 SCK0 SOUT1 SOUT0 SIN1 SIN0 tslsh tslov tivsh tshix tshsl ...

Page 59: ... to TXD0 TXCLK 0 15 ns RXDV setup time tsu_rxdv RXDV RXCLK 2 ns RXSV Hold Time thd_rxdv RXDV RXCLK 3 ns RXD setup time tsu_rxd RXD3 to RXD0 RXCLK 2 ns RXD Hold Time thd_rxdv RXD3 to RXD0 RXCLK 3 ns RXERsetup time tsu_rxer RXER RXCLK 2 ns RXER Hold Time thd_rxer RXER RXCLK 3 ns TXCLK TXEN TXD3 to TXD0 tdel_txen tdel_txd X 5 5 TXCLK TXEN TXD3 to TXD0 tdel_txen tdel_txd X n n 1 ...

Page 60: ...MB91401 60 Reception RXCLK RXDV RXD3 to RXD0 thd_rxdv tsu_rxdv tsu_rxd thd_rxdv 0 5 5 RXCLK RXDV RXD3 to RXD0 thd_rxdv tsu_rxdv tsu_rxd thd_rxdv 0 n n 1 RXCLK RXER tsu_rxer tsu_rxer thd_rxer thd_rxer ...

Page 61: ...MDIO delay time tdel_mdio MDIO MDCLK 10 30 ns MDIO switching time IN OUT tdel_turnon MDIO MDCLK 10 30 ns MDIO switching time OUT IN tdel_turnoff MDIO MDCLK 10 30 ns MDCLK MDIO INPUT tsu_mdio thd_mdio tsu_mdio thd_mdio MDCLK MDIO OUTPUT tdel_mdio tdel_mdio MDCLK MDIO INPUT OUTPUT tdel_turnon Input Mode Output Mode MDCLK MDIO OUTPUT INPUT tdel_turnoff Input Mode Output Mode ...

Page 62: ...Pin Value Unit Remarks Min Max EX Read Cycle time texrc EXA EXCSX 6 tcp ns EXA to Data Valid texadv EXA EXD 5 tcp ns EXCSX to Data Valid texcsdv EXCSX EXD 5 tcp ns EXRDX to Data Out Enable texdoe EXRDX EXD 5 tcp ns EXRDX H to High Z texdhz EXRDX EXD 5 tcp 8 ns texrc texadv texcsdv texdoe EXD15 to EXD0 texdhz EXA EXCSX EXWRX EXRDX ...

Page 63: ...Max EX Write Cycle time texwc EXA EXCSX 5 tcp ns EXA to Data Setup time texads EXA EXD 4 tcp ns EXCSX to Data Setup time texcsds EXCSX EXD 4 tcp ns EXWRX L Pulse width texwp EXRDX EXD 4 tcp ns EXD Setup time texds EXRDX EXD 11 ns EXD Hold time texdh EXRDX EXD 0 ns texwc texads texcsds texwp texds EXD15 to EXD0 texdhz EXA EXCSX EXWRX EXRDX tchdv ...

Page 64: ...0 Ω 15 The USB Standard stipulates that the USB driver s output impedance must be within the range of 28 Ω to 44Ω The USB Standard also stipulates that a discrete serial resistor RS must be added to have balance while satisfying the above standard The output impedance of the USB I O buffer on this LSI is about 3 Ω to 19 Ω Serial resistor RS to be added must be 25 Ω to 30 Ω 27 Ω recommended Capacit...

Page 65: ...D 3 State Full speed Buffer Rs Rs 28 Ω to 44 Ω Equiv Imped 28 Ω to 44 Ω Equiv Imped CL 50 pF CL 50 pF Notes Driver output impedance 3 Ω to 19 Ω Rs series resistance 25 Ω to 30 Ω Add a series resistor of preferably 27 Ω ...

Page 66: ...L pulse time twlscli SCL 4 7 µs SCL input setup time ts2scli SCL 4 µs SCL input hold time th2scli SCL 4 7 µs Parameter Symbol Pin Value Unit Remarks Min Max SCL output cycle time tcsclo SCL 2 m 2 PCLK SCL output H Pulse Time twhsclo SCL m 2 PCLK SCL output L Pulse Time twlsclo SCL m PCLK SCL output setup time ts2sclo SCL m 2 PCLK SCL output hold time th2sclo SCL m 2 PCLK SDA output hold time th2sd...

Page 67: ...Data Valid tcfadv CFA10 to CFA0 CFD15 to CFD0 ns CFCEX to Data Valid tcfcedv CFCE2X CFCE1X CFD15 to CFD0 ns CFOEX CFIORDX to Data Out Enable tcfdoe CFOEX CFIORDX CFD15 to CFD0 ns CFOEX CFIORDX H to High Z tcfdhz CFOEX CFIORDX CFD15 to CFD0 ns tcfrc tcfadv tcfcedv tcfdoe CFA10 to CFA0 CFCE2X CFCE1X CFWEX CFIOWRX CFD15 to CFD0 CFOEX CFIORDX tcfdhz ...

Page 68: ...CFA10 to CFA0 CFD15 to CFD0 ns CFCEX to Data Setup time tcfceds CFCE2X CFCE1X CFD15 to CFD0 ns CFWEX CFIOWRX L Pulse width tcffwp CFWEX CFIOWRX ns CFD Setup time tcfds CDWEX CFIOWRX CFD15 to CFD0 ns CFD Hold time tcfdhz CDWEX CFIOWRX CFD15 to CFD0 ns tcfwc tcfads tcfceds tcffwp tcfds CFA10 to CFA0 CFCE2X CFCE1X CFWEX CFIOWRX CFD15 to CFD0 CFOEX CFIORDX tcfdhz ...

Page 69: ...MB91401 69 ORDERING INFORMATION Part number Package Remarks MB91401 240 pin plastic FBGA BGA 240P M01 ...

Page 70: ... The values in parentheses are reference values C 1999 FUJITSU LIMITED B240001S 2C 2 10 00 0 10 394 004 SQ INDEX AREA 044 Ð 004 008 Ð0 10 0 20 1 13 Mounting height 0 25 0 10 Stand off 010 004 0 10 004 9 00 354 REF 0 50 020 TYP 240 0 30 0 10 240 012 004 M 0 05 002 W V U T R P N M L K J H G F E D C B A 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 INDEX ...

Page 71: ...MB91401 71 MEMO ...

Page 72: ... shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of Fujitsu or any third party or does Fujitsu warrant non infringement of any third party s intellectual property right or other right by using such information Fujitsu assumes no liability for any infringement of the intellectual property rights or othe...

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