Fujitsu MB91150 Series, Hardware Manual, Page: 42 / 512

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CHAPTER 2 HANDLING THE DEVICE
2.2 Notes on Using Devices
This section provides notes on using external reset input and external clocks.
■
External reset input
To securely put the device into the reset state, at least five machine cycles of L level input to the
RST pin are required.
■
External clock
When an external clock is used, feed the clock to the X0 pin and antiphase clock to the X1 pin
simultaneously. However, when the STOP mode (oscillation stop mode) is also used, the X1 pin
stops with H output in STOP mode. To prevent output collision, provide an external resistor of
about 1 k
Ω
.
Figure 2.2-1 "Example of using an external clock" shows an example of using an external clock.
Figure 2.2-1 Example of using an external clock
■
Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-
oscillating circuit even when there is no external oscillator or external clock input is stopped.
Performance of this operation, however, cannot be guaranteed.
■
Watchdog timer function
The watchdog timer supported by the FR family monitors the program that performs the reset
delay operation for a specified time. If the program hangs and the reset delay operation is not
performed, the watchdog timer resets the CPU. Therefore, once the watchdog timer is enabled,
operation continues until the CPU is reset.
As an exception, a reset delay automatically occurs if the CPU stops program execution. For the
conditions that apply to this exception, refer to the section that describes the watchdog function.
M B 9 1 1 5 0
X 0
X 1