Fujitsu MB91150 Series, Hardware Manual, Page: 207 / 512

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CHAPTER 7 16-BIT RELOAD TIMER
7.3.1 Control status register (TMCSR)
This register controls the operation mode and interrupts of the 16-bit timer.
Bits other than UF, CNTE, and TRG can be rewritten only when CNTE = 0.
Concurrent writing can be performed.
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Control status register (TMCSR)
The register configuration of the control status register (TMCSR) is shown below.
[Bits 11, 10] CSL1, CSL0 (Counter clock select)
These are counter clock select bits.
Table 7.3-1 "Clock sources and CSL bits" lists the clock sources that can be selected.
[Bits 9, 8, 7] MOD2, MOD1, MOD0 (MODe)
These bits set the operation mode.
All bits must be set to 0.
[Bits 6] OUTE (OUTput Enable)
This is an output enable bit. When this bit is set to 0, the TO pin becomes a general-purpose
port and when it is set to 1, the TO pin becomes a timer output pin.
The output waveform becomes toggled output at the reload mode and rectangular output at
the one-shot mode.
[Bit 5] OUTL:
This bit set the output level of the TO pin. The output level reverses in case of setting the bit
to 0 or 1.
11 10 9 8 7 6 5 4 3 2 1 0
TMCSR CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Initial value
Address: 000032
H
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
-000
H
00003A
H
000042
H
00004A
H
Table 7.3-1 Clock sources and CSL bits
CSL1 CSL0 Clock source (
φφφφ
: machine clock)
0 0
φ
/2
1
0 1
φ
/2
3
1 0
φ
/2
5
1 1 Setting prohibited