Fujitsu MB91150 Series, Hardware Manual, Page: 108 / 512

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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
3.12.2 Sleep Status
Sleep status means the stoppage of the CPU clock and internal bus clock.
This status can reduce power consumption to some extent when no CPU operation is
necessary.
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Block diagram of the sleep control block
Figure 3.12-2 "Block diagram of the sleep control block" shows a block diagram of the sleep
control block.
Figure 3.12-2 Block diagram of the sleep control block
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Transition to the sleep status
To enter the sleep status, set bit 7 of STCR to 0 and bit 6 to 1.
After a sleep request is issued, the CPU enters a status in which it is not using the internal bus.
After this, the clocks stop in the following order:
CPU clock --> internal bus clock
Note:
To enter the sleep status, be sure to use the following routines:
1. Before writing to STCR, set the [CCK1, CCK0] and [PCK1, PCK0] bits of GCR to the same
value and then set the gear ratios of the CPU system clock and peripheral system clock to
the same value.
2. The value of the GCR CHC bit is arbitrary.
3. At least six consecutive NOP instructions are required immediately after writing to STCR.
SLEP
STCR
clear
Sleep status transition
request signal
Stop signal
Internal bus
Status transition control circuit
Status decoder
CPU
clock
generation
CPU clock
Internal interrupt
Internal reset
Internal
bus clock
generation
Internal clock generation circuit
Internal bus clock
Internal DMA clock
External bus clock
Internal
peripheral
clock
generation
Internal
DMA
clock
generation
External
clock
generation
Internal peripheral clock
Sleep status display signal
Clock stop
request signal
Clock release
request signal