Fujitsu MB91150 Series, Hardware Manual, Page: 100 / 512

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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
3.11.11 Example of Setting the PLL Clock
This section gives an example of setting the PLL clock and also provides an example
of the related assembler source code.
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Example of setting the PLL clock
Figure 3.11-9 "Example of setting the PLL clock" gives an example of the procedure for
switching to 33-MHz operation using the PLL.
Figure 3.11-9 Example of setting the PLL clock
Notes:
• No particular setting order of the DBLON, VSTP, and SLCT1 bits shown here was specified
in the example.
• For a restart of PLL VC0, be sure to program a wait time of at least 300
µ
s to ensure
stabilization.
Ensure that the wait time does not become insufficient by cache ON or OFF operations.
WAIT 300 s
Before making the PLL-related settings, be sure to
switch to the clock signal of the divided-by-2
system.
The gear is fixed to CPU = 1/1 by setting the
doubler to ON. The peripheral system can be set
arbitrarily.
(Note: If no external bus is used, the doubler need
not be used. In this case, the CPU gear can
arbitrarily be set as well.)
If the PLL stops, it restarts automatically. However,
for PLL restart, the software needs a stabilization
wait time of 300 s or more.
The output tap from the PLL is switched to 33 MHz.
The clock is switched from the divided-by-2 system
to the PLL system.
CHC <-- 1
DBLON = 1
CHC = 1
DBLON <-- 1
DBLACK = 1
VSTP = 0
VSTP <-- 0
SLCTO <-- 1
CHC <-- 0
Yes
Yes
Yes
Yes
No
No
No
No