Fujitsu MB90460 Series, Hardware Manual, Page: 594 / 739

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CHAPTER 21 ROM CORRECTION FUNCTION
21.3.1 Program Aaddress Detection Register (PADR0/PADR1)
The program address detection register (PADR0/PADR1) is a 24-bit register and used to
store the address to be compared with internal address bus.
■
Program Address Detection Register 0/1 (PADR0/PADR1)
Figure 21.3-2 Program Address Detection Register 0/1
The value written to this register is compared with a target address. If the value matches the address, and
the corresponding interrupt enable bit of the PACSR register is "1", the corresponding interrupt bit is set to
"1" to request the CPU to generate an INT9 instruction. If the corresponding interrupt enable bit is "0", no
operation is performed.
Table 21.3-1 lists the correspondence between the program address detection register and PACSR.
Address : 1FF2
H
/1FF1
H
/1FF0
H
Address : 1FF5
H
/1FF4
H
/1FF3
H
Upper byte Middle byte Lower byte
PADR1
Program Address Detection Register 0/1
(XXXXXXXX
B
)
Initial value
(R/W) (R/W) (R/W)
Read/write
(XXXXXXXX
B
)
(XXXXXXXX
B
)
PADR0
PADRL0 PADRM0
PADRH0
PADRL1 PADRM1
PADRH1
Table 21.3-1 Correspondence between Program Address Detection Register and PACSR
Program address detection register Interrupt enable bit Interrupt bit
PADR0 AD0E AD0D
PADR1 AD1E AD1D