Fujitsu MB90460 Series, Hardware Manual, Page: 501 / 739

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CHAPTER 17 UART
17.4.4 Input Data Register (SIDR0/SIDR1) and Output Data
Register (SOR0/SOR1)
The input data register (SIDR0/SIDR1) is a serial data reception register. The output
data register (SODR0/SODR1) is a serial data transmission register. Both SIDR0/SIDR1
and SODR0/SODR1 registers are located in the same address.
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Input Data Register (SIDR0/SIDR1)
Figure 17.4-5 shows the bit configuration of input data register 1.
Figure 17.4-5 Input Data Register (SIDR0/SIDR1)
SIDR0/SIDR1 is a register that contains receive data. The serial data signal transmitted to the SIN0/SIN1
pin is converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7)
contains invalid data. When receive data is stored in this register, the receive data full flag bit (SSR0/
SSR1: RDRF) is set to "1". If a reception interrupt request is enabled at this point, a reception interrupt
occurs.
Read SIDR0/SIDR1 when the RDRF bit of the status register (SSR0/SSR1) is "1". The RDRF bit is
cleared automatically to "0" when SIDR0/SIDR1 is read.
Data in SIDR0/SIDR1 is invalid when a reception error occurs (SSR0/SSR1: PE, ORE or FRE = 1).
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Output Data Register (SODR0/SODR1)
Figure 17.4-6 shows the bit configuration of the output data register.
Figure 17.4-6 Output Data Register (SODR0/SODR1)
D3 D2 D1 D0 D4
7 6 5 4 3 2 1 0
D5 D7 D6
Serial input data register
SIDR0
SIDR1
(X) (X) (X) (X) (X) (X) (X) (X)
Initial value
(R) (R) (R) (R) (R) (R) (R) (R)
Read/write
Address : 000022
H
000026
H
bit
D3 D2 D1 D0 D4
7 6 5 4 3 2 1 0
D5 D7 D6
Serial output data register
SODR0
SODR1
(X) (X) (X) (X) (X) (X) (X) (X) Initial value
(W) (W) (W) (W) (W) (W) (W) (W) Read/write
Address : 000022
H
000026
H
bit